28HS01GTAM03 datasheet(55/138 Pages) INFINEON

55 / 138 page

Datasheet

55 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Features

4.8.1

Read identification transactions

There are three unique identification transactions, and each support all three Protocols (1S-1S-1S), (8S-8S-8S),

and (8D-8D-8D) (see Transaction table on page 95).

4.8.1.1

Read device identification transaction

The Read Device Identification (RDIDN_0_0, RDIDN_4_0) transaction provides read access to manufacturer

identification and device identification. The SPI mode has no address cycles, whereas the Octal mode has four

dummy addresses (00h). The transaction uses latency cycles set by (CFR3V[7:6]) to enable maximum clock

frequency of 166MHz under SPI mode, 166MHz under HL-T Octal, and 200MHz under HS-T Octal mode (see

Table 49). The Octal mode supports the DS for capture of data (see Transaction table on page 95).

4.8.1.2

Read SFDP transaction

The Read Serial Flash Discoverable Parameters (RSFDP_3_0, RSFDP_4_0) transaction provides access to the

JEDEC Serial Flash Discovery Parameters (SFDP) (see Transaction table on page 95). The transaction uses a

3-byte address in SPI mode and 4-byte address in Octal mode address. If a non-zero address is set, the selected

location in the SFDP space is the starting point of the data read. This enables random access to any parameter in

the SFDP space. Continuous (sequential) read is supported with this transaction. Eight latency cycles are

required. Read SFDP Transaction is not supported in Read Password mode before the password is provided. The

maximum clock frequency for the Read SFDP transaction is 156MHz under SPI mode, 92MHz under Octal SDR

mode, and 85MHz under Octal DDR mode.

4.8.1.3

Read unique identification transaction

Read Unique Identification (RDUID_0_0, RDUID_4_0) transaction is similar to Read Device Identification trans-

action, but accesses a different 64-bit number, which is unique to each device. It is factory programmed.

4.8.1.4

Read identification related register and transaction

4.8.2

Read memory array transactions

Memory array data can be read from the memory starting at any byte boundary. Data bytes are sequentially read

from incrementally higher byte addresses until the host ends the data transfer by driving CS# input HIGH. If the

byte address reaches the maximum address of the memory array, the read will continue at address zero of the

array.

4.8.2.1

SPI read and read fast transactions

The SPI Read and Read Fast transactions (1S-1S-1S) are supported for Host systems that require backward

compatibility to legacy SPI. This protocol does not support the DS for capture of data. The option of wrapped

read length is available. The Read transaction is for maximum clock frequency of 50MHz and requires no latency

cycles. The Read Fast Transaction uses latency cycles set by (CFR2V[3:0]) to enable maximum clock frequency of

166MHz (see Transaction table on page 95).

4.8.2.2

Octal data output read transactions (HL256T and HS256T only)

The Octal Data Output Read transactions (1S-1S-8S) are supported for Host systems that have the capability of

x8 data bus but still desire to send the command and address cycles in x1 serial mode. The option of wrapped

read length is available. This Read Transaction uses latency cycles set by (CFR2V[3:0]) to enable maximum clock

frequency of 166MHz (see Transaction table on page 95).

Table 29

Read identification related registers and transactions

Related registers

Related SPI transactions

(see Table 75 on page 95)

Related octal transactions

(see Table 78 on page 99)

Configuration Register 3 (CFR3N, CFR3V)

(see

Table 50 on page 82)

Read Identification (RDIDN_0_0)

Read Identification (RDIDN_4_0)

Configuration Register 5 (CFR5N, CFR5V)

(see

Table 54 on page 85)

Read Serial Flash Discoverable (RSFDP_3_0)

Read Serial Flash Discoverable (RSFDP_4_0)

Read Unique Identification (RDUID_0_1)

Read Unique Identification (RDUID_4_1)

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