FS26 datasheet(29/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

15 General device operation

15.1 Functional device operation and power modes

FS26 operation is divided in two independent logic blocks to achieve best-in-class functional safety coverage.

The main state machine manages the power management, the Low-power modes, and the wake-up sources,

while the fail-safe state machine manages the monitoring of the power management, the monitoring of the

microcontroller, and the monitoring of an external IC with ERRMON.

The FS26 provides three main operating modes:

• Normal mode is intended to be the fully functional mode. All power supplies are enabled as required by the

system, and all system functionality provided by the FS26 is available. During normal mode, the fail-safe state

machine is available and providing full monitoring and operation of all the safety features in the device.

• Standby mode is intended to be the Low-power ON mode, providing support to the minimum system

requirements with low current consumption from the battery. During the standby mode, only the VPRE

remains enabled to supply the microcontroller I/O rails. LDO1 and LDO2 can be enabled in this mode

depending on the OTP configuration. GPIO1 and GPIO2 can remain at the same state as in normal mode,

depending on the SPI configuration. standby mode is assumed to be a safe state with no critical activity, and

therefore the fail-safe state machine is disabled to achieve minimum current consumption by the system.

• LPOFF mode is intended to be the Low-power OFF mode, with no active system supplies except GPIO1,

which can remain enabled. Logic circuitry is internally supplied to allow proper wake up from any of the

available wake-up mechanisms, with the minimum current consumption possible.

The system can wake up from any of the Low-power modes via any of the following selectable wake-up

mechanisms available in the device (availability is dependent on part number):

• WAKE1 and WAKE2 pins

• GPIO1 and GPIO2 pins

• Long-duration timer (LDT) expiration

• SPI activity via edge detection of the CSB pin

Table 10 summarizes the operating modes and available features:

Power supply state

Wake-up sources and capabilities

Operating

mode

VPRE

LDOx

GPIOx

VBST, VCORE

TRK1, TRK2, VREF

WAKEx,

GPIOx

LDT

MCU

Normal mode

PWM, ON

(Optional)

N/A

Standby mode

PFM, ON

(Optional)

OFF

YES

(Optional)

YES

LPOFF mode

OFF

(GPIO1 optional)

OFF

YES

(Optional)

Table 10. Operating modes summary

The FS26 can also move to or through these two states:

• Load fuse state is a transitional state where the device loads its complete OTP configuration, previously

programmed in its fuses. The Main and the Fail-safe state machines both have to go through this state when

resuming from a power-up event.

• Deep Fail Safe (DFS) state is the device protection state. In this state, all regulators are OFF, safety outputs

are asserted, the SPI interface is not accessible. The device waits for specific events to restart and to move

to load fuse state to restart, and the safety outputs remain asserted until release conditions are met. DFS

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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