FS26 datasheet(95/156 Pages) NXP

95 / 156 page

NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

VBST_IN

VBST

VBST_ILIM_TH / RSNS_BST

Maximum IBST

180 mV / 20 mΩ

1.9 A

150 mV / 20 mΩ

1.7 A

120 mV / 20 mΩ

1.4 A

6 V

60 mV / 20 mΩ

0.7 A

180 mV / 20 mΩ

1.65 A

150 mV / 20 mΩ

1.45 A

120 mV / 20 mΩ

1.2 A

7 V

60 mV / 20 mΩ

0.6 A

180 mV / 20 mΩ

1.45 A

150 mV / 20 mΩ

1.25 A

120 mV / 20 mΩ

1.05 A

2.7 V

8 V

60 mV / 20 mΩ

0.5 A

Table 102. Maximum VBST output current in front-end configuration (DCBST_MAX = 87.5 %, DBST = 0.7 V, LSRDSON

= 50 mΩ, LBST_DCR = 60 mΩ)

In back-end mode or boost not used (VBST_CFG_OTP = 1):

In the back-end configuration, VBST can be supplied by VPRE or by an external supply. When VBST is

supplied by an external supply (VSUP, for example), the maximum duty cycle could limit the output current

capability and/or the delta voltage between VBST_IN and VBST.

In the back-end configuration, the output voltage is set by VBST_OTP[4:0] and NXP recommends setting

VBST_OV_OTP = 1 (overvoltage protection). In Overvoltage Protection mode, VBST will be disabled if an

overvoltage is detected (VBST > VBST_OV_TH). An SPI command is needed to turn on VBST again.

VBST_PG is indicating a boost overload during soft start or in normal operation. The power good pin

(VBST_PG) can be used to avoid an undervoltage cascading effect at the VBST input (VPRE) by opening

the VBST current path. This overload protection feature will require the external circuitry described in the

application note AN12995.

During a soft start, VBST_PG is at the high level (open drain OFF) to enable the external switch and

propagate the output voltage to the load. If an overload condition is detected (VBST < VBST_UV_PG), while the

minimum duty cycle is not reached, the VBST power good pin is asserted low to warn of the overload event.

The BOOST controller remains enabled until completion of soft start.

In normal operation, VBST_PG is at the high level (open drain OFF) when the output voltage remains in an

acceptable range and at the low level (open drain ON) when the output voltage is 25 % below its nominal

voltage (VBST < VBST_UV_PG).

The VBST current limitation is sensed at the input, and therefore the current capability can be estimated

depending on VBST_IN, VBST voltage configuration and the external components (LBST, RSNS_BST, DBST). As

an example, Table 103 summarizes the maximum current capability for an input average current of 500 mA

using LBST = 4.7 µH and the recommended RSNS_BST for COUT_BST = 40 µF.

When the boost controller is not used in the application, VBST_CFG_OTP and VSUP_UVTH_OTP should

both be set to 1. The unused pins should be handled as described in Connection of unused pins.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

Document feedback

95 / 156

FS26 Datenblatt(PDF) 95 Page - NXP Semiconductors

FS26 Datenblatt(HTML) 95 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL