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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 47 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 47 Page - NXP Semiconductors |
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47 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B Bit Symbol Value Description Central temperature sensor thermal warning flag Set when TJ > TWARN 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 15 TWARN_I Reset on power-on reset (POR_M) or clear on write 1 GPIO1 thermal shutdown flag. Set when local TJ > TSDGPIO1 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 6 GPIO1TSD_I Reset on power-on reset (POR_M) or clear on write 1 VPRE thermal shutdown flag. Set when local TJ > TSDPRE 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 5 VPRETSD_I Reset on power-on reset (POR_M) or clear on write 1 TRK2 thermal shutdown flag. Set when local TJ > TSDTRKx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 4 TRK2TSD_I Reset on power-on reset (POR_M) or clear on write 1 TRK1 thermal shutdown flag. Set when local TJ > TSDTRKx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 3 TRK1TSD_I Reset on power-on reset (POR_M) or clear on write 1 VCORE thermal shutdown flag. Set when local TJ > TSDCORE 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 2 CORETSD_I Reset on power-on reset (POR_M) or clear on write 1 LDO2 thermal shutdown flag. Set when local TJ > TSDLDOx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 1 LDO2TSD_I Reset on power-on reset (POR_M) or clear on write 1 LDO1 thermal shutdown flag. Set when local TJ > TSDLDOx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 0 LDO1TSD_I Reset on power-on reset (POR_M) or clear on write 1 Table 23. M_TSD_FLG register bit description 16.2.5 M_TSD_MSK Bit 15 14 13 12 11 10 9 8 Write TWARN_M 0 0 0 0 0 0 0 Read TWARN_M RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset 0 0 0 0 0 0 0 0 Table 24. M_TSD_MSK register bit allocation Bit 7 6 5 4 3 2 1 0 Write 0 GPIO1TSD_M VPRETSD_M TRK2TSD_M TRK1TSD_M CORETSD_M LDO2TSD_M LDO1TSD_M Read RESERVED GPIO1TSD_M VPRETSD_M TRK2TSD_M TRK1TSD_M CORETSD_M LDO2TSD_M LDO1TSD_M Reset 0 0 0 0 0 0 0 0 FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 47 / 156 |
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