FS26 datasheet(39/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

Bit

Symbol

Description

Event reported in the M_REG_FLG register

Reset on power-on reset (POR_M), cleared when all individual bits are cleared

Source Register: M_REG_FLG

Flags Reporting: VBSTOV_I, VPREUVH_I, VPREOC_I, TRK2OC_I, TRK1OC_I, COREOC_I,

LDO2OC_I, LDO1OC_I, VBSTOC_I

Event notification from the M_TSD_FLG register

No event reported in M_TSD_FLG register

Event reported in the M_TSD_FLG register

Reset on power-on reset (POR_M), cleared when all individual bits are cleared

Source Register: M_TSD_FLG

TSD_G

Flags Reporting: TWARN_I, GPIO1TSD_I, VPRETSD_I, TRK2TSD_I, TRK1TSD_I,

CORETSD_I, LDO2TSD_I, LDO1TSD_I

Table 12. MISO general device status bit descriptions...continued

15.6.1 Cyclic redundancy check

An 8-bit cyclic redundancy check (CRC) is required for each Write and Read SPI command. Computation

of a cyclic redundancy check is derived from the mathematics of polynomial division, modulo two. The CRC

polynomial used is x^8+x^4+x^3+x^2+1 (identified by 0x1D) with a SEED value of hexadecimal '0xFF'.

Figure 22 is an example of CRC encoding HW implementation:

aaa-046864

1*1

0*X

1*X2

1*X3

1*X4

0*X5

0*X6

0*X7

1*X8

Input

Data

Figure 22. CRC encoder example

The effect of the CRC encoding procedure is shown in Table 13. The seed value is appended into the most

significant bits of the shift register.

Seed

M/FS

Read/Write

DATA_MSB

DATA_LSB

0xFF

Bit[31]

Bits[30:25]

Bit[24]

Bits[23:16]

Bits[15:8]

Table 13. Data preparation for CRC encoding

1. Using a serial CRC calculation method, the transmitter rotates the seed and data into the least significant

bits of the shift register.

2. During the serial CRC calculation, the seed and the data bits are XOR compared with the polynomial data

bits. When the MSB is logic 1, the comparison result is loaded in the register, otherwise the data bits are

simply shifted. It must be noted the 32-bit message to be processed must have the bits corresponding to the

CRC byte all equal to zero (00000000).

3. Once the CRC is calculated, the initial CRC byte composed of zeros is replaced and the CRC is transmitted.

Procedure for CRC decoding:

1. The seed value is loaded into the most significant bits of the receive register.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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