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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 69 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 69 Page - NXP Semiconductors |
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69 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B Bit Bit Group Name Description Value Settings 1h DFS entry disabled 0h 16 MHz 1h 17 MHz 2h 18 MHz 6 to 5 CLK_FREQ_OTP[1:0] Clock frequency selection FOSC_HIGH 3h 19 MHz 0h Bypass disabled 1h Bypass slot 1 to 6 2h Bypass slot 2 to 6 3h Bypass slot 3 to 6 4h Bypass slot 4 to 6 5h Bypass slot 5 to 6 6h Bypass slot 6 4 to 2 SLOT_BYP_OTP[2:0] Power-up slot bypass 7h Bypass disabled 0h 250 µs 1h 500 µs 2h 1000 µs 1 to 0 TSLOT_OTP[1:0] Power up slot time 3h 2000 µs Table 70. OTP_SYS_CFG2 register bit description...continued Go to main OTP configuration map 17.2.3 OTP_SYS_CFG3 Bit Bit Group Name Description Value Settings 0h GPIO2 is not driven by VCORE_PGOOD 7 GPIO2_VCORE_PGOOD_OTP GPIO2 VCORE_PGOOD 1h GPIO2 is driven by VCORE_PGOOD 0h GPIO2 LS active high 6 GPIO2_MODE_OTP GPIO2 Low Side polarity 1h GPIO2 LS active low 0h GPIO1 LS active high 5 GPIO1_MODE_OTP GPIO1 Low Side polarity 1h GPIO1 LS active low 0h VREF pin lift detection enabled 4 VREF_PLIFT_DIS_OTP VREF pin lift detection 1h VREF pin lift detection disabled 0h LDO2 pin lift detection enabled 3 LDO2_PLIFT_DIS_OTP LDO2 pin lift detection 1h LDO2 pin lift detection disabled 0h LDO1 pin lift detection enabled 2 LDO1_PLIFT_DIS_OTP LDO1 pin lift detection 1h LDO1 pin lift detection disabled 0h Auto Transition from VPRE to VSUP when VPRE < VPRE_UVBOS 1 to 0 BOS_IN_OTP[1:0] BOS input selection 1h Force BOS input to VSUP always Table 71. OTP_SYS_CFG3 register bit description Go to main OTP configuration map 17.2.4 OTP_VBST_CFG1 Bit Bit Group Name Description Value Settings 7 to 6 VBST_MAX_DC_OTP[1:0] VBST maximum duty cycle 0h 72.5 % Table 72. OTP_VBST_CFG1 register bit description FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 69 / 156 |
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