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FS26 Datenblatt(PDF) 50 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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FS26 Datenblatt(HTML) 50 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
16.2.7 M_REG_MSK
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
VBSTOV_M
Read
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VBSTOV_M
Reset
0
0
0
0
0
0
0
0
Table 28. M_REG_MSK register bit allocation
Bit
7
6
5
4
3
2
1
0
Write
VPREUVH_M
VBSTOC_M
VPREOC_M
TRK2OC_M
TRK1OC_M
COREOC_M
LDO2OC_M
LDO1OC_M
Read
VPREUVH_M
VBSTOC_M
VPREOC_M
TRK2OC_M
TRK1OC_M
COREOC_M
LDO2OC_M
LDO1OC_M
Reset
0
0
0
0
0
0
0
0
Go to main register map
Bit
Symbol
Value
Description
Inhibit interrupt (INTB pulse) related to VBSTOV_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
8
VBSTOV_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VPREUVH_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
7
VPREUVH_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VBSTOC_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
6
VBSTOC_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VPREOC_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
5
VPREOC_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to TRK2OC_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
4
TRK2OC_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to TRK1OC_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
3
TRK1OC_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to COREOC_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
2
COREOC_M
Reset on power-on reset (POR_M)
Table 29. M_REG_MSK register bit description
FS26_SDS
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© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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