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FS26 Datenblatt(PDF) 89 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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FS26 Datenblatt(HTML) 89 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages
are referenced to ground.
Symbol
Description
Min
Typ
Max
Unit
ηPRE_PWM_PEAK[1]
Efficiency in PFM mode
COUT_PRE = 22 µF with ESR = 2 mΩ, LPRE = 10 µH with RDCR_LPRE =
60 mΩ, FPRE = 450 kHz
VSUP = VSUP_PWR = 12 V and 5.4 V
VPRE_PFM = 5.05 V with IPRE_PFM = 1 mA
VPRE_PFM_TON_OTP[1:0] = 10
—
90
—
%
RHS_PRE
High-side on-resistance
(VBOS = 5 V, including bonding)
—
310
500
mΩ
RLS_PRE
Low-side on-resistance
(VBOS = 5 V, including bonding)
—
170
300
mΩ
RPRE_DIS
Discharge resistor (when VPRE is disabled – LPOFF)
20
40
60
Ω
TSDPRE
Thermal shutdown threshold
175
—
—
°C
TSDPRE_HYST
Thermal shutdown threshold hysteresis
5
—
12
°C
DC overcurrent flag threshold in PWM mode (set VPREOC_I)
IPRE_OC_FLAG[2]
VPRE_OC_OTP[2:0] = 000
VPRE_OC_OTP[2:0] = 001
VPRE_OC_OTP[2:0] = 010
VPRE_OC_OTP[2:0] = 011
VPRE_OC_OTP[2:0] = 100
VPRE_OC_OTP[2:0] = 101
VPRE_OC_OTP[2:0] = 110
VPRE_OC_OTP[2:0] = 111
0.45
0.65
0.85
1.12
1.30
1.49
1.68
1.87
0.66
0.88
1.1
1.32
1.54
1.76
1.98
2.2
1.0
1.25
1.45
1.70
1.95
2.12
2.38
2.64
A
ILIM_PRE
VPRE output DC current limitation threshold in PWM mode
1.95
2.42
2.9
A
VPRE_OVP
Main overvoltage protection on VPRE output
(relative to VPRE output voltage setting)
20
25
30
%
Dynamic electrical characteristics
tPRE_OVP
Overvoltage deglitch time
1
2
3
µs
tPRE_DEAD
Dead time to avoid cross conduction
1
—
20
ns
Soft start ramp from 0 % to 100 % defined at IPRE_PWM = 0 A
tPRE_SS
VPRE_SS_OTP[1:0] = 00 (COUT_PRE ≤ 44 μF nominal)
VPRE_SS_OTP[1:0] = 01
VPRE_SS_OTP[1:0] = 10
VPRE_SS_OTP[1:0] = 11
200
431
873
1753
269
538
1077
2150
410
645
1281
2547
µs
DVS down ramp rate during low-power mode transition
VPRE_DVS_DOWN
VPRE_LP_DVS_OTP[1:0] = 00 (COUT_PRE ≤ 44 μF nominal)
VPRE_LP_DVS_OTP[1:0] = 01
VPRE_LP_DVS_OTP[1:0] = 10
VPRE_LP_DVS_OTP[1:0] = 11
18
9
4.5
2.25
22
11
5.5
2.75
27
13.5
6.75
3.375
mV/µs
VPRE_LINE_REG_450K_PWM
Transient line in PWM mode with FPRE = 450 kHz
VBAT = 6 V - 18 V – 6 V and 14 V - 35 V - 14 V
IPRE_PWM = 0 A and 1.5 A for VPRE_PWM = 3.3 V
IPRE_PWM = 0 A and 0.6 A for VPRE_PWM = 5.0 V
dV/dt = 100 mV/µs, LPRE = 10 μH,
CIN_PRE = 47 µF + PI filter, COUT_PRE = 44 μF
-1.5
—
1.5
%
VPRE_LINE_REG_450K_DO
Transient line after drop out exit with FPRE = 450 kHz
VBAT = VPRE_PWM - 0.4 V to 14 V
IPRE_PWM = 0 A and 0.6 A for VPRE_PWM = 5.0 V
dV/dt = 100 mV/µs, LPRE = 10 μH,
CIN_PRE = 47 µF + PI filter, COUT_PRE = 44 μF
-3
—
3
%
VPRE_LOTR_450K_PWM
Transient load response in PWM mode with FPRE = 450 kHz
10 mA to 800 mA step and 800 mA to 10 mA step
800 mA to 1.5 A step and 1.5 A to 800 mA step
di/dt = 300 mA/µs, COUT_PRE ≥ 22 µF, LPRE = 10 µH
-3
—
3
%
Table 100. VPRE electrical characteristics...continued
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
Document feedback
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