FS26 datasheet(33/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

• Once VSUP has crossed the VSUP_UVH threshold, VPRE is enabled automatically.

• The remaining regulators will start as set in the OTP power-up sequence configuration.

Direct connection to VSUP

• Once VSUP has crossed the VSUP_UVH threshold, VPRE is enabled automatically.

• The remaining regulators will start in their corresponding power-up slot as set in the OTP power-up sequence

configuration.

15.4.1 Regulator power-up sequence

Seven slots are available to program the startup sequence of VCORE, LDO1, LDO2, VREF, TRK1, and TRK2,

as well as the GPIO1 and GPIO2 signals for external control.

The power-up sequence starts from SLOT_0 to SLOT_6, with a TSLOT_OTP[1:0] delay between each slot.

RSTB is released after SLOT_6. Regulators assigned to SLOT_7 / OFF are not started during the power-up

sequence and can be enabled later in normal mode via a SPI command. When VBST is used in back-end

supply, it can only be enabled via a SPI command once the device is in normal mode.

Each regulator is assigned to a slot by OTP configuration using the dedicated OTP bits. Each slot is executed

regardless of whether a regulator is assigned to a slot or not. Slots can be bypassed with SLOT_BYP_OTP[2:0].

A regulator assigned to a bypassed slot will not start in the power-up sequence.

When the last power-up slot is completed, monitoring of the voltages is enabled. If the soft start of a regulator

is not achieved and the output voltage is still below the UV monitoring, the UV is detected and reported in the

corresponding flag. Therefore, NXP recommends clearing all the UV flags at each startup during initialization

phase.

When VCORE is enabled, the bootstrap capacitor must be charged. Therefore, the VCORE regulator output

starts to ramp-up with a delay of 100 µs from the beginning of the slot.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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FS26 Datenblatt(PDF) 33 Page - NXP Semiconductors