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FS26 Datenblatt(PDF) 58 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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FS26 Datenblatt(HTML) 58 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
Bit
7
6
5
4
3
2
1
0
Write
0
0
0
0
0
0
VREF_PD
VBST_TMD
Read
0
0
0
0
0
0
VREF_PD
VBST_TMD
Reset
0
0
0
0
0
0
1
0
Go to main register map
Bit
Symbol
Description
VREF Internal pull-down configuration (RREF_DIS)
0h  Disable internal pull-down when VREF output is disabled
1h  Enable internal pull-down when VREF output is disabled
1
VREF_PD
Reset on power-on reset (POR_M)
VBST output verification mode
h  VBST output is regulated to the configured voltage set by OTP
1h  VBST regulate to 17 V to verify availability
0
VBST_TMD
Reset on power-on reset (POR_M)
Table 47. M_REG_CFG register bit description (default value in bold)
16.2.17 M_WIO_CFG
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
GPIO2WUPOL
GPIO1WUPOL
WAKE2POL
WAKE1POL
Read
0
0
0
0
GPIO2WUPOL
GPIO1WUPOL
WAKE2POL
WAKE1POL
Reset
0
0
0
0
0
0
0
0
Table 48. M_WIO_CFG register bit allocation
Bit
7
6
5
4
3
2
1
0
Write
0
0
CSBWUEN
LDTWUEN
GPIO2WUEN
GPIO1WUEN
WK2WUEN
WK1WUEN
Read
0
0
CSBWUEN
LDTWUEN
GPIO2WUEN
GPIO1WUEN
WK2WUEN
WK1WUEN
Reset
0
0
0
0
0
0
0
0
Go to main register map
Bit
Symbol
Description
GPIO2 event detection polarity
0h  High level on GPIO2 will wake up the part
1h  Low level on GPIO2 will wake up the part
11
GPIO2WUPOL
Reset on power-on reset (POR_M)
GPIO1 event detection polarity
0h  High level on GPIO1 will wake up the part
1h  Low level on GPIO1 will wake up the part
10
GPIO1WUPOL
Reset on power-on reset (POR_M)
WAKE2 event detection polarity
0h  High level on WAKE2 will wake up the part
1h  Low level on WAKE2 will wake up the part
9
WAKE2POL
Reset on power-on reset (POR_M)
8
WAKE1POL
WAKE1 event detection polarity
Table 49. M_WIO_CFG register bit description (default value in bold)
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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