FS26 datasheet(86/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

18 Power management

18.1 BOS: best of supply regulator for internal biasing

The BOS regulator manages the Best Of Supply (BOS) from VSUP or VPRE to efficiently generate 5.0 V

output and to supply the internal biasing of the device. BOS supplies the high-side and low-side gate drivers of

switching regulators.

The VBOS_UVL detection threshold powers down the device.

When the device is starting up, BOS voltage, which is supplied by VSUP until normal mode state, needs to rise

above the VBOS_UVH threshold to move to load fuse state.

The BOS_IN_OTP[1:0] bits define the BOS supply voltage source when the device is in normal mode state:

• When the VPRE output voltage setting is above or equal to 5.0 V, it is recommended to BOS_IN_OTP[1:0] =

00 (auto transition). This setting will ensure an optimized power dissipation of the internal biasing.

• When the VPRE output voltage setting is below 5.0 V, it is recommended to have the BOS_IN_OTP[1:0] = 01

(force VBOS_IN = VSUP). This setting is not optimized for BOS power dissipation but will guarantee correct

operation of all switching mode power supplies (SMPS).

TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages

are referenced to ground.

Symbol

Description

Min

Typ

Max

Unit

Static electrical characteristics

VBOS_NORM

VBOS voltage range in normal mode

(VSUP > 4.5 V and VPRE_PWM > VPRE_UVBOS)

VPRE_UVBOS

- 0.2

5.5

VBOS_STBY

VBOS voltage range in standby mode

(VSUP > 4.5 V, 3.7 V < VPRE_PFM < 35 V)

VPRE_PFM

- 0.2

—

VPRE_PFM

VBOS_LPOFF

VBOS voltage range in LPOFF mode

(VSUP > 4.5 V)

2.9

4.5

5.5

VBOS_UVH

VBOS undervoltage threshold (rising edge)

3.8

4.0

4.2

VBOS_UVL

VBOS undervoltage threshold (falling edge)

3.2

3.4

VBOS_POR

VBOS power-on reset threshold

2.5

—

3.2

VDIG_POR

VDIG power-on reset threshold (POR_M condition)

1.35

—

1.54

VDIG_FS_POR

VDIG_FS power-on reset threshold (POR_FS condition)

1.35

—

1.54

External components

BOS output capacitor at VBOS pin

CBOS_OUT

Nominal[1] value

Effective[2] value

4.7

3.3

4.7

—

4.7

6.1

µF

VDIG output capacitor

CDIG_OUT

Nominal[1] value

Effective[2] value

0.75

—

1.25

µF

Table 98. BOS electrical characteristics

[1]

For all regulators, the nominal value is the value normalized.

[2]

For all regulators, the effective value is the value after tolerance, temperature, DC bias and aging removal.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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