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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 67 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 67 Page - NXP Semiconductors |
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67 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 17 OTP bits description 17.1 OTP overview Register Name ADDRESS (Hex) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 OTP_SYS_ CFG1 20 RETRY_MSK_OTP[3:0] RETRY_ MODE_OTP RETRY_ DIS_OTP WK1DFS_ DIS_OTP VSUP_ UVTH_OTP OTP_SYS_ CFG2 21 MDFS_DIS_OTP CLK_FREQ_OTP[1:0] SLOT_BYP_OTP[2:0] TSLOT_OTP[1:0] OTP_SYS_ CFG3 22 GPIO2_VCORE_ PGOOD_OTP GPIO2_ MODE_OTP GPIO1_ MODE_OTP VREF_PLIFT_ DIS_OTP LDO2_PLIFT_ DIS_OTP LDO1_PLIFT_ DIS_OTP BOS_IN_OTP[1:0] OTP_VBST_ CFG1 23 VBST_MAX_DC_OTP[1:0] — VBSTLS_ SR_OTP VBST_PH_OTP[1:0] VBST_ OV_OTP VBST_ CFG_OTP OTP_VBST_ CFG2 24 VBST_TON_MIN_OTP[1:0] VBST_RCOMP_OTP[1:0] VBST_CCOMP_OTP[1:0] VBST_GMCOMP_OTP[1:0] OTP_VBST_ CFG3 25 VBST_ILIM_OTP[1:0] VBST_SC_OTP[5:0] OTP_ VBST_VOLT 26 VBST_SS_OTP[1:0] — VBST_OTP[4:0] OTP_VPRE_ CFG1 27 VPRE_OC_OTP[2:0] VPRE_ SR_OTP VPRE_PH_OTP[1:0] VPRE_SS_OTP[1:0] OTP_VPRE_ CFG2 28 — VPRE_RCOMP_OTP[2:0] VPRE_CCOMP_OTP[1:0] VPRE_GM_OTP[1:0] OTP_VPRE_ CFG3 29 VPRE_OC_DGLT_OTP[1:0] VPRE_SC_OTP[5:0] OTP_VPRE_ CFG4 2A VPRETSD_ PD_OTP VPRETDFS_ OTP VPRE_ CLK_OTP — VPRE_PFM_TOFF_OTP[1:0] VPRE_PFM_ TON_OTP[1:0] OTP_VPRE_ VOLT1 2B — VPRE_OTP[5:0] OTP_VPRE_ VOLT2 2C VPRE_LP_DVS_OTP[1:0] VPRE_LP_OTP[5:0] OTP_VPRE_ VOLT3 2D VPRE_PDWN_DLY_OTP[1:0] VPRE_BOS_OTP[5:0] OTP_CORE_ CFG1 2E — COREHS_SR_OTP[1:0] CORE_PH_OTP[1:0] CORE_ILIM_OTP[1:0] OTP_CORE_ CFG2 2F — CORE_RCOMP_OTP[1:0] CORE_CCOMP_OTP[1:0] CORE_GM_OTP[1:0] OTP_CORE_ CFG3 30 — CORE_SS_OTP[1:0] 0 CORE_ CTRL_OTP CORE_LSEL_OTP[1:0] OTP_CORE_ VOLT1 31 VCORE_OTP[7:0] OTP_CORE_ CFG5 32 CORETSD_ PD_OTP CORETDFS_ OTP — CORE_SLOT_OTP[2:0] OTP_ LDO1_CFG 33 LDO1TSD_ PD_OTP LDO1 TDFS_OTP LDO1_LP_ EN_OTP VLDO1_ LP_OTP VLDO1_OTP LDO1_SLOT_OTP[2:0] OTP_ LDO2_CFG 34 LDO2TSD_ PD_OTP LDO2 TDFS_OTP LDO2_LP_ EN_OTP VLDO2_ LP_OTP VLDO2_OTP LDO2_SLOT_OTP[2:0] OTP_ TRK1_CFG 35 TRK1TSD_ PD_OTP TRK1 TDFS_OTP TRK1_SEL_OTP[1:0] — TRK1_SLOT_OTP[2:0] OTP_ TRK2_CFG 36 TRK2TSD_ PD_OTP TRK2 TDFS_OTP TRK2_SEL_OTP[1:0] — TRK2_SLOT_OTP[2:0] OTP_ VREF_CFG 37 — VLDO_REF_OTP[1:0] VREF_OTP VREF_SLOT_OTP[2:0] OTP_ GPIO1_CFG 38 GPIO1TSD_ PD_OTP GPIO1 PD_OTP GPIO1 PU_OTP GPIO1STAGE_OTP[1:0] GPIO1_SLOT_OTP[2:0] Table 68. Main OTP configuration map FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 67 / 156 |
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