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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 63 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 63 Page - NXP Semiconductors |
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63 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B Bit Symbol Value Description AMUX input channel selection 00h Disabled with AMUX pin in Hi-Z (default) 01h Low-power bandgap (voltage reference) 02h Main bandgap (voltage reference) 03h Fail-safe bandgap (voltage reference) 04h VANA: Internal main analog voltage supply 05h VDIG: internal main digital voltage supply 06h VDIG_FS: internal fail-safe digital voltage supply 07h VCORE feedback pin CORE_FB voltage 08h VPRE feedback pin VPRE_FB voltage 09h LDO1 feedback pin LDO1OUT voltage 0Ah LDO2 feedback pin LDO1OUT voltage 0Bh VREF feedback pin voltage 0Ch TRK1 feedback pin voltage 0Dh TRK2 feedback pin voltage 0Eh VDDIO feedback voltage 0Fh VBOS internal pin voltage 10h VBST feedback pin VBST_FB voltage (divider ratio configurable with AMUX_DIV) 11h VSUP pin voltage VSUP (divider ratio configurable with AMUX_DIV) 12h WAKE1 pin voltage (divider ratio configurable with AMUX_DIV) 13h WAKE2 pin voltage (divider ratio configurable with AMUX_DIV) 14h GPIO1 pin voltage (divider ratio configurable with AMUX_DIV) 15h GPIO2 pin voltage (divider ratio configurable with AMUX_DIV) 16h BATSENSE pin voltage (divider ratio configurable with AMUX_DIV) 17h Die temperature sensor[1] 18h VCORE temperature sensor[1] 19h VPRE temperature sensor[1] 1Ah LDO1 temperature sensor[1] 1Bh LDO2 temperature sensor[1] 1Ch TRK1 temperature sensor[1] 1Dh TRK2 temperature sensor[1] 1Eh GPIO1 temperature sensor[1] 1Fh Reserved 4 to 0 AMUX[4:0] Reset on power-on reset (POR_M) Table 55. M_AMUX_CTRL register bit description...continued [1] Temp (°C) = (VAMUX_OUT – VTEMP25) / VTEMP_COEFF + 25 16.2.21 M_LDT_CFG1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write LDT_AFTER_RUN[15:0] Read LDT_AFTER_RUN[15:0] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 56. M_LDT_CFG1 register bit allocation Go to main register map FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 63 / 156 |
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