FS26 datasheet(35/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

aaa-045457

VBAT

0 V

VBOS

VDIG

VPRE

SLOT_0

SLOT_1

SLOT_2

SLOT_3

SLOT_4

SLOT_5

SLOT_6

RSTB

TSLOT

ABIST (max 300 s)

VSUP>VSUP_UVH

VBOS_UVH

VDIG>1.45 V

VPRE>0.97xVPRE_OTP

TSLOT

Figure 18. Power-up example with direct battery supply

To reduce the power-up timing, SLOT_BYP_OTP[2:0] setting is provided to bypass the unused slots. Devices

slots jumps from the slot SLOT_BYP_OTP[2:0] to normal mode, bypassing SLOT_X to SLOT_6.

Once the power-up sequence is completed, the Main state machine is in normal mode, which is the application

running mode with all the regulators ON.

15.4.2 System power-down sequence

During a power-down event, the device uses the same slot bits to turn off the voltage regulators, in reverse

order from the power-up sequence.

If a slot bypass configuration is enabled, the device will start the power-down sequence from the selected slot in

the OTP configuration.

When powering down to the standby mode, VPRE remains enabled. LDO1 and LDO2 can be programmed to

also remain enabled during the standby mode. GPIO1 and GPIO2 can also remain in the same state that they

were in, in normal mode. All other regulators are disabled as defined by the slot bits.

When powering down into the LPOFF mode, all voltage regulators are disabled as described in the power-down

sequence. Once the voltage regulators in the sequencer are disabled, the VPRE will start powering off, followed

by the VBST if it is used as the front-end supply.

If VBST is used in back-end mode, the regulator will be turned off in the first power-down slot.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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