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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 97 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 97 Page - NXP Semiconductors |
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97 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages are referenced to ground. Symbol Description Min Typ Max Unit Nominal output current in front-end VBST_CFG_OTP = 0 (VBST configured as front-end supply) VBST ≤ 10 V and VBST_IN ≥ 2.7 V — 1 — A IBST Nominal output current in back-end VBST_CFG_OTP = 1 (VBST configured in back-end) VBST ≤ 18 V and VBST_IN ≥ 3.6 V (powered by VPRE) — — 0.5 A Voltage threshold to detect an inductor peak current limit condition Differential measurement at VBST_ISH pin and VBST_ISL pin VBST_ILIM_TH VBST_ILIM_OTP[1:0] = 00 VBST_ILIM_OTP[1:0] = 01 VBST_ILIM_OTP[1:0] = 10 VBST_ILIM_OTP[1:0] = 11 48 96 120 144 60 120 150 180 72 144 180 216 mV VBST_OV_TH Overvoltage threshold range (sensed on VBST_FB pin) 105 110 115 % VBSTG VBST_G driver output voltage VPRE_UVBOS - 0.2 VBOS 5.5 V RBSTG VBST_G driver pull-down (when VBST is disabled) 6 14.5 23 kΩ VBST_G current drive at VBOS = 5 V and VBSTG = VBOS / 2 IBSTG VBSTLS_SR_OTP = 0 VBSTLS_SR_OTP = 1 0.7 0.9 — — 2.0 3.4 A VBST_UV_TH Undervoltage threshold range (sensed on VBST_FB pin) 1.3 1.5 1.7 V VBST_UV_PG VBST undervoltage threshold range to assert VBST_PG pin in back-end mode (sensed on VBST_FB pin) 72.5 75 77.5 % RBST_PG_PU External pull-up resistor to VDDIO pin 5 10 20 kΩ VBST_PG_VOL Low output level threshold (IBST_PG = 2.0 mA) — — 0.4 V IBST_PG_LEAK Input leakage current — — 1.0 µA Dynamic electrical characteristics FBST Switching frequency range 380 450 500 kHz tBST_UVOV VBST_UV_TH, VBST_OV_TH filtering time 5 10 15 µs Maximum duty cycle DCBST_MAX VBST_MAX_DC_OTP[1:0] = 00 VBST_MAX_DC_OTP[1:0] = 01 VBST_MAX_DC_OTP[1:0] = 10 VBST_MAX_DC_OTP[1:0] = 11 — — — — 72.5 77.5 82.5 87.5 — — — — % Soft start from VBST enable to 90 % tBST_SS VBST_SS_OTP[1:0] = 00 VBST_SS_OTP[1:0] = 01 VBST_SS_OTP[1:0] = 10 VBST_SS_OTP[1:0] = 11 — 425 850 1700 3400 600 1200 2400 4800 µs Digital DAC soft start completion (delay from VBST enable in front-end to VPRE enable) tBST_SS_DAC VBST_SS_OTP[1:0] = 00 VBST_SS_OTP[1:0] = 01 VBST_SS_OTP[1:0] = 10 VBST_SS_OTP[1:0] = 11 — 1150 2300 4600 9200 1250 2500 5000 10100 µs VBST_LINE_ON VBST transient line in front end configuration always ON VBAT = 3.2 V - 6.5 V - 3.2 V dV/dt = 100 mV/μs , LBST = 4.7 μH, IBST = 0 A and 1 A CIN_BST_FE = 47 µF, COUT_BST_FE = 50 μF -5 — 5 % Table 104. VBST electrical characteristics...continued FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 97 / 156 |
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