FS26 datasheet(87/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

18.2 VPRE: high-voltage buck regulator

The VPRE block is a high-voltage integrated synchronous buck. It operates in forced PWM or PFM modes, and

uses internal FETs. The output voltage and the switching frequency (450 kHz or 2.25 MHz) are configurable by

OTP. Compensation is ensured by internal circuitry.

VPRE can be used to supply VCORE, LDO1, LDO2, TRK1, TRK2, VREF, and the VBST. VPRE can also supply

local loads inside the ECU.

At startup, VPRE soft start can be configured through VPRE_SS_OTP[1:0] bits. In case VPRE is supplied by a

pre-regulator (not FS26 VBST), the slowest soft start must be used VPRE_SS_OTP[1:0] = 11.

VPRE operates in PWM (pulse width modulation) when the FS26 is in normal mode and in PFM (pulsed

frequency modulation) when the FS26 is in standby mode. The transition from PWM mode to PFM mode is

ensured by a controlled DVS down ramp configurable by OTP (VPRE_DVS_DOWN).

The current in the inductor is sensed through both high-side and low-side switches. The output DC current

is then deducted for internal treatment. When the current in the inductor is rising above the IPRE_OC_FLAG

threshold, the SPI bit VPREOC_I is set. This overcurrent detection does not affect VPRE regulation.

VPRE has a DC current limitation protection feature ILIM_PRE. When VPRE reaches its current limitation, it

induces a duty cycle reduction and therefore an output voltage drop. If the overcurrent disappears before

reaching VPRE_UVL, the regulator restarts by doing a soft start toward its nominal output voltage.

To protect the circuitry that is supplied by the VPRE power rail, an additional overvoltage protection is integrated

in the main domain. If VPRE_PWM > VPRE_OVP for a time longer than tPRE_OVP, the FS26 goes directly into the

Deep Fail Safe state.

VPRE_IN (VSUP_PWR) must be above VPRE_PWM + VPRE_HDR to guarantee VPRE output voltage regulation and its

trip level. It can be configured through the VPRE_OC_OTP[2:0] bits.

A thermal shutdown protection is integrated to protect the internal MOSFETs from damage. In case of a TSD

event, a pull-down resistor (RPRE_DIS) is enabled to discharge VPRE output capacitors.

The transition from normal mode to LPOFF mode is ensured by a controlled DVS down ramp (VPRE_DVS_DOWN)

until VPRE is disabled. A power down delay can be configured through VPRE_PDWN_DLY_OTP[1:0]

bit to avoid immediate restart. The delay is executed as soon as VPRE DVS down is completed. VPRE

regulator is not intended to restart with residual voltage. Therefore, when VPRE is operating at 2.25 MHz,

VPRE_PDWN_DLY_OTP[1:0] bit must be configured according to NXP recommendations, as shown in

Table 99.

ASIL level

VBST configuration

@VPRE_PDWN_DLY_OTP[1:0]

Front-end

—

Back-end / not used

≥ 1 ms

Front-end

≥ 2 ms

Back-end / not used

5 ms

Table 99. VPRE power-down delay configuration when FPRE = 2.25 MHz

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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