FS26 datasheet(4/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

aaa-045445

FS26

FUNCTIONAL BLOCK DIAGRAM

VBST (CONTROLLER)

5.0 V TO 18 V

VCORE

0.8 V TO 3.35 V

@ 0.8 A OR 1.65 A

LDO1 (LP)

3.3 V OR 5.0 V @ 0.4 A

LDO2 (LP)

3.3 V OR 5.0 V @ 0.4 A

TRK1

INTERNAL LDO REFERENCE/

VREF/LDO2 @ 150 mA

TRK2

INTERNAL LDO REFERENCE/

VREF/LDO2 @ 150 mA

VOLTAGE SUPERVISOR

CLOCK MANAGEMENT

FIT FOR ASIL D

SAFETY LOGIC AND

CONTROL SPI,

INDEPENDENT

SAFETY MONITORING

UNIT

AMUX (I/O, TEMP,

VREF, BATSENSE)

OTP

CONFIGURATION

LOGIC AND CONTROL

POWER-UP

SEQUENCING

SPI, LOW POWER

INTERNAL LDO

REFERENCE

1.2 V/1.8 V/3.3 V/5.0 V

VREF

3.3 V/5.0 V (±0.75 %)

@ 30 mA

SELECTABLE WAKE-UP

WAKE PINS

GPIO (LP)

LDT

SPI

LATENT FAULT CHECK

ABIST ON DEMAND

OTP - iSMU

WINDOW WATCHDOG

(SIMPLE/CHALLENGER)

S32 HW FAILURE

MONITOR (FCCU)

IC HW

FAILURE MONITORING

VPRE HVBUCK - INTERNAL MOSFETs

CONFIGURABLE FROM 3.7 V TO 6.35 V @ 1.5 A

SAFETY OUTPUTS (RSTb, FS0b, FS1b)

ISOLATION

Figure 1. Functional block diagram

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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