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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 37 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 37 Page - NXP Semiconductors |
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37 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B • Bit 24: Read/Write (for reading bit 24 = 0; for writing bit 24 = 1) • Bits 23 to 8: Control bits • Bits 7 to 0: Cyclic redundant check (CRC) MISO (Main In, Secondary Out) bits: • Bits 31 to 24: General device status (see Table 12) • Bits 23 to 8: Extended device status, or device internal control register content or device flags • Bits 7 to 0: Cyclic redundant check (CRC) The digital SPI pins (CSB, SCLK, MOSI, MISO) are referenced to VDDIO. The MCU is the primary driving MOSI and FS26 is the secondary driving MISO. The MISO data is latched at the SCLK rising edge and MOSI data is latched at the SCLK falling edge, MSB first. In a write command, MISO[23:8] bits are the previous register bits and MISO[7:0] is the CRC of the message sent by the FS26. In a read command, MOSI[23:8] bits are all 0 and MOSI[7:0] is the CRC of the message sent by the MCU. Figure 20 and Figure 21 describe the SPI communication protocol for writing data into the FS26 or reading data from the FS26. The FS_EN bit is set high as soon as the fail-safe state machine enters Enable monitoring state. The bit remains enabled during the normal operation until the system has successfully moved into any of the low power states. In all other states, FS_EN = 0. The M_AVAL bit is set high as soon as the main state machine is in normal mode state. In all other states, this bit is set to 0. aaa-045511 MOSI MISO M/FS REG_ADDRESS [5:0] B31 M_AVAL B30 FS_EN B29 FS_G B28 COM_G B27 WIO_G B26 VSUP_G B25 REG_G B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R/W DATA_MSB[7:0] DATA_LSB[7:0] CRC[7:0] CRC[7:0] - response TSD_G Figure 20. SPI write operation protocol aaa-045512 MOSI MISO M/FS REG_ADDRESS [5:0] B31 M_AVAL B30 FS_EN B29 FS_G B28 COM_G B27 WIO_G B26 VSUP_G B25 REG_G B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R/W READ_DATA_MSB[7:0] READ_DATA_LSB[7:0] CRC[7:0] CRC[7:0] - response TSD_G Figure 21. SPI read operation protocol Bit Symbol Description Device domain access 0 Main domain register map 31 M/FS 1 Fail-safe domain register map Register address 30 to 25 REG_ADDESS[5:0] See Table 15 for main domain register mapping Operation requested 0 Read 24 R/W 1 Write 23 to 8 DATA[15:0] Register data 7 to 0 CRC[7:0] Cyclic redundancy check data sent by MCU Table 11. MOSI general bit description FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 37 / 156 |
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