FS26 datasheet(30/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

state entry can be disabled by setting MDFS_DIS_OTP = 1 and DFS_DIS_OTP = 1, transition request

sources listed hereafter will be ignored, however the safety pins are asserted accordingly with fault sources

and reactions configuration.

Below is an exhaustive list of conditions that put the FS26 in the Deep Fail Safe state:

• RSTB pin is sensed to low level for a time longer than 8 seconds.

• Too many faults occur: fault error counter reaches its programmed limit (FLT_ERR_CNT[3:0] =

@FLT_ERR_CNT_LIMIT[1:0]).

• When FAULT_DFS_EN_OTP = 1 the device enters the Deep Fail Safe state upon detection of an RSTB or

FS0B fault, regardless of the actual states of the RSTB or FS0B pins.

• VPRE output voltage crosses VPRE_OVP threshold for a time longer than tPRE_OVP.

• Each regulator is disabled when an overtemperature event is detected, that is thermal shutdown (TSD).

Additionally, the TSD event can be configured with M_TSD_CFG register to lead device to Deep Fail Safe

state (for instance VPRETSD_I = 1 and VPRETDFS = 1).

Below is an exhaustive list of conditions that make the device leave the Deep Fail Safe state for the load fuse

state:

• WAKE1 event: resumes if WK1DFS_DIS_OTP = 0 and WAKE1 pin is toggled from low to high or from high to

low logic level.

• Infinite auto-retry mode: the FS26 makes attempts to resume periodically and RETRY_CNT[7:0] increments

every try. Once the RETRY_CNT[7:4] reaches the RETRY_MSK_OTP[3:0] value, the RETRY_CNT[7:0] time

value is clamped and retries occur infinitely to the last clamped retry frequency (RETRY_MSK_OTP[3:0]) until

a valid resume condition is detected. The OTP configuration to select this mode is RETRY_DIS_OTP = 0 and

RETRY_MODE_OTP = 1.

• Limited auto-retry mode: the FS26 makes attempts to resume while RETRY_CNT[7:4] is smaller than

RETRY_MSK_OTP[3:0]. When the RETRY_CNT[7:4] reaches the RETRY_MSK_OTP[3:0] value, the

FS26 stays in the Deep Fail Safe state until a power-on reset event occurs (VBOS < VBOS_POR). The OTP

configuration to select this mode is RETRY_DIS_OTP = 0 and RETRY_MODE_OTP = 0.

Example: the first time the device enters Deep Fail Safe state, it will try to exit this state every 100 ms, and

RETRY_CNT[7:0] increments at each attempt. After 16 consecutive failed attempts, RETRY_CNT[7:4]

increments and the counter uses the next value of 200 ms, and so on, until RETRY_CNT[7:4] =

RETRY_MSK_OTP[3:0].

Note: the retry counter RETRY_CNT[7:0] is divided in two parts. RETRY_CNT[7:4] represents the timing

the counter is currently using (100 ms, 200 ms, and so on) and RETRY_CNT[3:0] is the number of attempts

performed at the current used timing. RETRY_CNT[7:0] can be read as the total number of attempts performed

by the device since the first Deep Fail Safe entry.

15.2 Application flowchart

In an application, the debug pin is connected to ground and a watchdog refresh is required as soon as the

initialization phase is closed. The system enters normal mode once the safety outputs are released. Figure 14 is

a high-level flowchart illustrating entry into normal mode in the application.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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