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FS26 Datenblatt(PDF) 52 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
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FS26 Datenblatt(HTML) 52 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
16.2.9 M_VSUP_MSK
Bit
15
14
13
12
11
10
9
8
Write
0
0
0
0
0
0
0
0
Read
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Reset
0
0
0
0
0
0
0
0
Table 32. M_VSUP_MSK register bit allocation
Bit
7
6
5
4
3
2
1
0
Write
0
0
0
0
VBOSUVH_M
VSUPOV_M
VSUPUV6_M
VSUPUVH_M
Read
RESERVED
RESERVED
RESERVED
RESERVED
VBOSUVH_M
VSUPOV_M
VSUPUV6_M
VSUPUVH_M
Reset
0
0
0
0
0
0
0
0
Go to main register map
Bit
Symbol
Value
Description
Inhibit interrupt (INTB pulse) related to VBOSUVH_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
3
VBOSUVH_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VSUPOV_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
2
VSUPOV_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VSUPUV6_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
1
VSUPUV6_M
Reset on power-on reset (POR_M)
Inhibit interrupt (INTB pulse) related to VSUPUVH_I event
0h
Interrupt NOT MASKED (default)
1h
Interrupt MASKED
0
VSUPUVH_M
Reset on power-on reset (POR_M)
Table 33. M_VSUP_MSK register bit description
16.2.10 M_WIO_FLG
Bit
15
14
13
12
11
10
9
8
Write
WU_CLR
0
0
0
0
0
0
0
Read
RESERVED
RESERVED
RESERVED
RESERVED
WUEVENT[3:0]
Reset
0
0
0
0
0
0
0
0
Table 34. M_WIO_FLG register bit allocation
Bit
7
6
5
4
3
2
1
0
Write
0
0
0
0
0
0
0
0
Read
RESERVED
RESERVED
RESERVED
LDT_I
GPIO2_I
GPIO1_I
WK2_I
WK1_I
Reset
0
0
0
0
0
0
0
0
Go to main register map
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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