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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 42 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 42 Page - NXP Semiconductors |
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42 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 16 Register mapping 16.1 Register map overview Register Name ADDRESS (Hex) BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 M_ DEVICEID 00 FULL_LAYER_REV [15:13] METAL_LAYER_REV [12:10] FAM_ID [9:6] DEV_ID [5:0] M_PROGID 01 PROG_IDH [15:8] PROG_IDL [7:0] M_STATUS 02 TWARN_S VDBG_ VOLT_S VBST_ ACTIVE_S VBSTFB_ UV_S WK2_S WK1_S GPIO2_S GPIO1_S VREF_S VBST_S VPRE_S TRK2_S TRK1_S CORE_S LDO2_S LDO1_S M_TSD_ FLG 03 TWARN_I 0 0 0 0 0 0 0 0 GPIO1TSD_I VPRETSD_ I TRK2TSD_I TRK1TSD_I CORETSD_I LDO2TSD_I LDO1TSD_I M_TSD_ MSK 04 TWARN_M 0 0 0 0 0 0 0 0 GPIO1 TSD_M VPRETSD_ M TRK2 TSD_M TRK1 TSD_M CORETSD_ M LDO2 TSD_M LDO1TSD_M M_REG_ FLG 05 0 0 0 0 0 0 0 VBSTOV_ I VPREUVH_ I VBSTOC_I VPREOC_I TRK2OC_I TRK1OC_I COREOC_I LDO2OC_I LDO1OC_I M_REG_ MSK 06 0 0 0 0 0 0 0 VBSTOV_ M VPREUVH_ M VBSTOC_M VPREOC_ M TRK2OC_M TRK1OC_M COREOC_M LDO2OC_M LDO1OC_M M_VSUP_ FLG 07 0 0 0 0 0 0 0 0 0 0 0 0 VBOSUVH_I VSUPOV_I VSUPUV6_I VSUPUVH_I M_VSUP_ MSK 08 0 0 0 0 0 0 0 0 0 0 0 0 VBOSUVH_ M VSUPOV_M VSUPUV6_ M VSUPUVH_ M M_WIO_ FLG 09 WU_CLR 0 0 0 WUEVENT [11:8] 0 0 0 LDT_I IO2_I IO1_I WK2_I WK1_I M_WIO_ MSK 0A 0 0 0 0 0 0 0 0 0 0 0 LDT_M IO2_M IO1_M WK2_M WK1_M M_COM_ FLG 0B 0 0 0 0 0 0 0 0 0 0 0 0 0 MSPI_CRC_I MSPI_CLK_I MSPI_REQ_I M_COM_ MSK 0C 0 0 0 0 0 0 0 0 0 0 0 0 0 MSPI_ CRC_M MSPI_ CLK_M MSPI_ REQ_M M_SYS_ CFG 0D RETRY_CNT [15:8] RETRY_ CLR 0 0 INTB_TEST INT_ PWIDTH FSS_FMOD 0 FSS_EN M_TSD_ CFG 0E 0 0 0 0 0 0 0 0 0 0 VPR ETDFS TRK2TDFS TRK1TDFS CORETDFS LDO2TDFS LDO1TDFS M_REG_ CFG 0F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF_PD VBST_TMD M_WIO_ CFG 10 0 0 0 0 GPIO2 WUPOL GPIO1 WUPOL WAKE2 POL WAKE1 POL 0 0 CSBWUEN LDTWUEN GPIO2 WUEN GPIO1WUEN WK2WUEN WK1WUEN M_REG_ CTRL1 11 0 0 GPIO2LP_ON GPIO1LP_ON 0 0 GPIO2HI GPIO1HI VREFEN VBSTEN 0 TRK2EN TRK1EN COREEN LDO2EN LDO1EN M_REG_ CTRL2 12 0 IO2LO IO1LO VREFDIS VBSTDIS 0 TRK2DIS TRK1DIS COREDIS LDO2DIS LDO1DIS M_AMUX_ CTRL 13 0 0 0 0 0 0 0 0 0 AMUX_EN AMUX_DIV AMUX [4:0] Table 15. Main SPI register map overview FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 42 / 156 |
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