FS26 datasheet(32/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

VPRE

VBST

VBST_G

VBAT

VBST_ISH

VBST_ISL

VPRE

VBST

COUT_PRE

CBOOT

LVPRE

COUT_BST

CIN_BST_FE

CBAT

DBAT

DBST

LBST

RSNS_BST

aaa-045451

VBST_FB

Figure 15. Input topology: front-end boost controller

When VSUP < VBST, the boost controller starts switching to maintain VSUP above the VSUP_UVH threshold,

thus ensuring system operation during crank profiles.

2. For systems with less severe or no cranking events, the input power can be applied directly to the VSUP

pin. In this scenario, the FS26 can ensure functionality if VSUP > VPREPWM + VPRE_HDR (Section 18.2 for

VPRE_HDR). The device will shut down if VPREPWM < VPRE_UVL. The reverse voltage protection diode and a

PI-filter are needed to guarantee optimal EMI performance.

aaa-045452

VPRE

VBAT

COUT_PRE

CBOOT

LVPRE

Cpi2

Cpi1

CBAT

DBAT

Lpi

Figure 16. Input topology: direct VSUP connection

At the chip level, the power-up sequencing and operating thresholds are referenced to VSUP input.

However, proper considerations should be made to ensure the system level requirements are met with

respect to VBAT voltage.

15.4 System power-up and power-down

When a voltage is applied to the VSUP pin, the FS26 starts its internal power-up biasing. As the internal best

of supply (BOS) reaches regulation and the default OTP configuration is loaded, the system proceeds to turn

on the output regulators based on the OTP configuration of the device. The regulators' power-up sequence is

dependent on the input power topology used in the system:

With VBST used as the front-end supply

• VBST is enabled first and will ensure VSUP > VSUP_UVH.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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