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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 40 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 40 Page - NXP Semiconductors |
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40 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 2. Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least significant bits of the shift register in the order received (MSB first). 3. When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the CRC check result. • If the shift register contains all zeros, the CRC is correct. • If the shift register contains a value other than zero, the CRC is incorrect. 15.6.2 SPI electrical characteristics and timing diagram TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages are referenced to ground. Symbol Description Min Typ Max Unit Interface I/O input supply VDDIO VDDIO supply voltage range 3.0 — 5.5 V Static Electrical Characteristics VSPI_VIL CSB, SCLK, MOSI low level input voltage threshold — — 0.3 x VDDIO V VSPI_VIH CSB, SCLK, MOSI high level input voltage threshold 0.7 x VDDIO — — V RSCLK_IPD SCLK internal pull-down current source 7 10 13 µA VMISO_VOH MISO high output voltage (I = 2.0 mA) VDDIO - 0.4 — — V VMISO_VOL MISO low output voltage (I = 2.0 mA) — — 0.4 V IMISO_LEAK 3-state leakage current (VDDIO = 5.0 V) - 5.0 — 5.0 µA RSPI_PU CSB, MOSI internal pull-up (pull-up to VDDIO) 190 450 800 kΩ CSPI Input capacitor at CSB, SCLK, MOSI — — 10 pF Dynamic Electrical Characteristics FSPI SPI operation frequency (50 % DC) 0.5 — 10 MHz tCLH Minimum time SCLK = HIGH 50 — — ns tCLL Minimum time SCLK = LOW 50 — — ns tPCLD Propagation delay (SCLK to data at 10 % of MISO rising edge) — — 30 ns tCSDV CSB = low to data at MISO active — — 70 ns tSCLCH SCLK low before CSB low (setup time SCLK to CSB change H/L) 70 — — ns tHCLCL SCLK change L/H after CSB = low 70 — — ns tSCLD SDI input setup time (SCLK change H/L after MOSI data valid) 35 — — ns tHCLD SDI input hold time (MOSI data hold after SCLK change H/L) 35 — — ns tSCLCL SCLK low before CSB high 90 — — ns tHCLCH SCLK high after CSB high 90 — — ns tPCHD CSB L/H to MISO at high-impedance — — 75 ns tONCSB CSB min. high time 500 — — ns tCBS_MIN CSB filter time 10 — 40 ns Table 14. SPI Electrical characteristics FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 40 / 156 |
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