28HS01GTAM03 datasheet(101/138 Pages) INFINEON

101 / 138 page

Erase flash

array

ER004_4_0

Erase 4-KB Sector trans-

action sets all the bits of a 4KB

sector to 1 (all bytes are FFh).

WRENB_

0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 20/

Figure 21

166 / 200

ER256_4_0

Erase 256-KB Sector trans-

action sets all the bits of a

256KB sector to 1 (all bytes

are FFh).

WRENB_

0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

ERCHP_0_0

Erase Chip transaction sets

all bits to 1 (all bytes are FFh)

inside the entire flash

memory array.

WRENB_

0_0

60 or

(CMD)

60 or

(CMD)

Figure 18/

Figure 19

N/A

EVERS_4_0

Evaluate Erase Status trans-

action verifies that the last

erase operation on the

addressed sector was

completed successfully.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 20/

Figure 21

SEERC_4_0

Sector Erase Count trans-

action outputs the number of

erase cycles for the sector of

the inputed address from the

Sector Erase Count Register.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Suspend /

resume

SPEPD_0_0

Suspend Erase / Program /

Data Integrity Check trans-

action allows the system to

interrupt a programming,

erase or data integrity check

operation

(CMD)

Figure 18/

Figure 19

N/A

RSEPD_0_0

Resume Erase / Program /

Data Integrity Check trans-

action allows the system to

resumeaprogramming,erase

or data integrity check

operation

(CMD)

Secure

silicon

region

PRSSR_4_1

Program Secure Silicon

Region transaction programs

data in 1024 bytes of Secure

Silicon Region

WRENB_

0_0

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Input

Data 1

[7:0]

Input

Data 2

[7:0]

(Conti

nue)

Figure 24/

Figure 25

RDSSR_4_0

Read Secure Silicon Region

transaction reads data from

the SSR.

(CMD)

ADDR

[31:24]

ADDR

[23:16]

ADDR

[15:8]

ADDR

[7:0]

Figure 27/

Figure 28

Table 78

Octal (8S-8S-8S, 8D-8D-8D) transaction table (Continued)

Note

32. In case of Octal DDR protocol.

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