28HS01GTAM03 datasheet(137/138 Pages) INFINEON

137 / 138 page

Datasheet

137 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Revision history

Document

version

Date of

release

Description of changes

2019-07-03

Finalizing document for S28HS512T and S28HL512T devices description.

2019-09-13

Updated Transaction Table.

Updated Ordering Information.

2019-12-20

Finalizing document for S28HS01GT devices.

Note: The characterization of 200MHz, S28HS01GT devices is in progress and this document will be updated

accordingly upon characterization completion.

Updated Table 18, Table 83, Table 85, Table 87 (Product Information Notification), Table 89 (Product Information

Notification), and Table 90, Table 92, and Table 93.

Updated typos in Table 45, Table 50, and Table 60.

2020-01-29

Finalizing document for S28HL01GT devices.

Updated Sales information and Copyright year.

2020-03-23

Updated Table 83 based on Final Characterization results.

2020-04-22

Updated Table 9 and Table 58.

Updated Table 87 and Table 89 (Product Information Notification).

2020-12-10

Updated Selected options for CFR3N[7:6], CFR3V[7:6 in Table 50.

Updated RDPLB_4_0, RDIDN_4_0, RDSR1_4_0, and RDSR2_4_0 in Table 51.

Added note in Table 51.

Updated description and data for ASPO[2] in Table 59.

Renamed ASPPAS to ASPPWD for ASPO[2] in Table 61.

Updated Input Timing Ref Voltage and Input Timing Ref Voltage to 0.5 VCC in Table 84.

Updated Figure 72, Figure 73, and Figure 74 in Timing reference levels.

Removed volatile register address for 1EAh SFDP Byte in Table 87.

Updated from CFR3N[3], CFR1N[2], and CFR1N[6] to CFR3V[3], CFR1V[2], and CFR1V[6] in Sector map parameter table

notes.

Updated Sector map parameters in Table 88.

Updated SFDP data and description in Table 89.

2021-08-10

Updated DC table (

Table 83).

Updated

Ordering information on page 134.

Updated OPN tables (

Table 92 and Table 93).

2021-10-18

Updated to Infineon template.

Updated Transaction protocol on page 11, Read transactions on page 54, Program on page 60.

Added Octal output interface (Octal, 1S-1S-8S and 1S-8S-8S) (HL256T and HS256T only) on page 16, SPI

(1S-1S-8S) transaction table (HL256T and HS256T only) on page 98, SPI (1S-8S-8S) transaction table (HL256T and

HS256T only) on page 98 for new features Octal Output (1S-1S-8S), Octal Input (1S-8S-8S) HL256T and HS256T only.

Updated Table 83: Added 256Mb specifications.

Updated Table 84: Added 256Mb specifications.

Updated Table 80: Added Theta JB an Theta JC.

2022-01-18

Updated Table 6: Changed JESD216C to JESD216D

Changed CFR3V[1:0] to CFR3V[7:6] in Read device identification transaction

Updated Table 85: Removed 256T / 512T / 01GT and updated max value for tPEDS

Updated Figure 73 and Figure 74: Changed PSCK to PCK

Updated Table 87: Updated data and description for 12Dh, 12Eh, and 12Fh byte addresses

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