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FS26 Datenblatt(PDF) 152 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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FS26 Datenblatt(HTML) 152 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
Tables
Tab. 1.
Device segmentation .......................................10
Tab. 2.
Orderable production part numbers ................ 11
Tab. 3.
Pin descriptions ...............................................15
Tab. 4.
Maximum ratings .............................................17
Tab. 5.
ESD ................................................................. 18
Tab. 6.
Temperatures ranges ...................................... 19
Tab. 7.
Thermal resistance (per JEDEC JESD51-2) ... 19
Tab. 8.
Electrical characteristics ..................................21
Tab. 9.
Electrical characteristics ..................................25
Tab. 10. Operating modes summary .............................29
Tab. 11. MOSI general bit description ...........................37
Tab. 12. MISO general device status bit descriptions ....38
Tab. 13. Data preparation for CRC encoding ................39
Tab. 14. SPI Electrical characteristics ...........................40
Tab. 15. Main SPI register map overview ..................... 42
Tab. 16. M_DEVICEID register bit allocation ................ 44
Tab. 17. M_DEVICEID register bit description .............. 44
Tab. 18. M_PROGID register bit allocation ................... 44
Tab. 19. M_PROGID register bit description ................. 44
Tab. 20. M_STATUS register bit allocation ....................45
Tab. 21. M_STATUS register bit description ..................45
Tab. 22. M_TSD_FLG register bit allocation ................. 46
Tab. 23. M_TSD_FLG register bit description ............... 47
Tab. 24. M_TSD_MSK register bit allocation ................ 47
Tab. 25. M_TSD_MSK register bit description
(default value in bold) ..................................... 48
Tab. 26. M_REG_FLG register bit allocation .................48
Tab. 27. M_REG_FLG register bit description ...............49
Tab. 28. M_REG_MSK register bit allocation ................50
Tab. 29. M_REG_MSK register bit description ..............50
Tab. 30. M_VSUP_FLG register bit allocation ...............51
Tab. 31. M_VSUP_FLG register bit description .............51
Tab. 32. M_VSUP_MSK register bit allocation ..............52
Tab. 33. M_VSUP_MSK register bit description ............52
Tab. 34. M_WIO_FLG register bit allocation ................. 52
Tab. 35. M_WIO_FLG register bit description ............... 53
Tab. 36. M_WIO_MSK register bit allocation ................ 53
Tab. 37. M_WIO_MSK register bit description
(default) ........................................................... 54
Tab. 38. M_COM_MSK register bit allocation ............... 54
Tab. 39. M_COM_MSK register bit description
(default value in bold) ..................................... 54
Tab. 40. M_COM_FLG register bit allocation ................ 55
Tab. 41. M_COM_FLG register bit description ..............55
Tab. 42. M_SYS_CFG register bit allocation .................55
Tab. 43. M_SYS_CFG register bit description ...............56
Tab. 44. M_TSD_CFG register bit allocation .................57
Tab. 45. M_TSD_CFG register bit description ...............57
Tab. 46. M_REG_CFG register bit allocation ................ 57
Tab. 47. M_REG_CFG register bit description
(default value in bold) ..................................... 58
Tab. 48. M_WIO_CFG register bit allocation .................58
Tab. 49. M_WIO_CFG register bit description
(default value in bold) ..................................... 58
Tab. 50. M_REG_CTRL1 register bit allocation ............ 59
Tab. 51. M_REG_CTRL1 register bit description .......... 60
Tab. 52. M_REG_CTRL2 register bit allocation ............ 61
Tab. 53. M_REG_CTRL2 register bit description .......... 61
Tab. 54. M_AMUX_CTRL register bit allocation ............62
Tab. 55. M_AMUX_CTRL register bit description ..........62
Tab. 56. M_LDT_CFG1 register bit allocation ............... 63
Tab. 57. M_LDT_CFG1 register bit description .............64
Tab. 58. M_LDT_CFG2 register bit allocation ............... 64
Tab. 59. M_LDT_CFG2 register bit description .............64
Tab. 60. M_LDT_CFG3 register bit allocation ............... 64
Tab. 61. M_LDT_CFG3 register bit description .............64
Tab. 62. M_LDT_CTRL register bit allocation ............... 65
Tab. 63. M_LDT_CTRL register bit description ............. 65
Tab. 64. M_MEMORY0 register bit allocation ............... 65
Tab. 65. M_MEMORY0 register bit description ............. 66
Tab. 66. M_MEMORY1 register bit allocation ............... 66
Tab. 67. M_MEMORY1 register bit description ............. 66
Tab. 68. Main OTP configuration map .......................... 67
Tab. 69. OTP_SYS_CFG1 register bit description ........ 68
Tab. 70. OTP_SYS_CFG2 register bit description ........ 68
Tab. 71. OTP_SYS_CFG3 register bit description ........ 69
Tab. 72. OTP_VBST_CFG1 register bit description ...... 69
Tab. 73. OTP_VBST_CFG2 register bit description ...... 70
Tab. 74. OTP_VBST_CFG3 register bit description ...... 70
Tab. 75. OTP_VBST_VOLT register bit description .......72
Tab. 76. OTP_VPRE_CFG1 register bit description ......73
Tab. 77. OTP_VPRE_CFG2 register bit description ......73
Tab. 78. OTP_VPRE_CFG3 register bit description ......74
Tab. 79. OTP_VPRE_CFG4 register bit description ......74
Tab. 80. OTP_VPRE_VOLT1 register bit description .... 75
Tab. 81. OTP_VPRE_VOLT2 register bit description .... 76
Tab. 82. OTP_VPRE_VOLT3 register bit description .... 77
Tab. 83. OTP_CORE_CFG1 register bit description ..... 78
Tab. 84. OTP_CORE_CFG2 register bit description ..... 78
Tab. 85. OTP_CORE_CFG3 register bit description ..... 79
Tab. 86. OTP_CORE_VOLT1 register bit description ....79
Tab. 87. OTP_CORE_CFG5 register bit description ..... 79
Tab. 88. OTP_LDO1_CFG register bit description ........ 80
Tab. 89. OTP_LDO2_CFG register bit description ........ 80
Tab. 90. OTP_TRK1_CFG register bit description ........ 81
Tab. 91. OTP_TRK2_CFG register bit description ........ 81
Tab. 92. OTP_VREF_CFG register bit description ........82
Tab. 93. OTP_GPIO1_CFG register bit description .......82
Tab. 94. OTP_GPIO2_CFG register bit description .......83
Tab. 95. OTP_INPUT_CFG register bit description .......83
Tab. 96. OTP_PROG_IDH register bit description ........ 84
Tab. 97. OTP_PROG_IDL register bit description .........85
Tab. 98. BOS electrical characteristics ..........................86
Tab. 99. VPRE power-down delay configuration
when FPRE = 2.25 MHz ................................. 87
Tab. 100. VPRE electrical characteristics ....................... 88
Tab. 101. VPRE efficiency in forced PWM mode ............ 92
Tab. 102. Maximum VBST output current in front-
end configuration (DCBST_MAX = 87.5 %,
DBST = 0.7 V, LSRDSON = 50 mΩ, LBST_
DCR = 60 mΩ) ................................................95
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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