FS26 datasheet(154/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

Figures

Fig. 1.

Functional block diagram .................................. 4

Fig. 2.

Example of application diagram with VBST

as a front-end regulator .................................... 7

Fig. 3.

Example of application diagram with VBST

as a back-end regulator .................................... 8

Fig. 4.

Part number breakdown ....................................9

Fig. 5.

Part number mapping versus features set .........9

Fig. 6.

Block diagram of the FS26 ..............................14

Fig. 7.

Pin assignment in LQFP48 package with

exposed pad ....................................................15

Fig. 8.

Input voltage range in normal mode ................23

Fig. 9.

Input voltage range in standby mode and

LPOFF mode () ...............................................24

Fig. 10.

Battery current consumption in standby

mode (LDO1 and LDO2 disabled) ...................26

Fig. 11.

LDOx current consumption in standby

mode ............................................................... 26

Fig. 12.

Total battery current consumption in

standby mode ..................................................27

Fig. 13.

Battery current consumption in standby

mode with VPRE_PFM = 3.70 V or 5.35 V

and LDOx disabled ......................................... 28

Fig. 14.

Application flowchart ....................................... 31

Fig. 15.

Input topology: front-end boost controller ........ 32

Fig. 16.

Input topology: direct VSUP connection .......... 32

Fig. 17.

Power-up example with VBST as front-end

supply .............................................................. 34

Fig. 18.

Power-up example with direct battery

supply .............................................................. 35

Fig. 19.

Power-down example with VBST as front-

end supply .......................................................36

Fig. 20.

SPI write operation protocol ............................37

Fig. 21.

SPI read operation protocol ............................ 37

Fig. 22.

CRC encoder example ....................................39

Fig. 23.

SPI timing diagram ..........................................41

Fig. 24.

VPRE schematic with connection to VSUP ..... 88

Fig. 25.

VPRE efficiency at VPRE_CLK_OTP = 0 ........92

Fig. 26.

VPRE efficiency at VPRE_CLK_OTP = 1 ........93

Fig. 27.

VBST schematic with configuration from

VPRE ...............................................................96

Fig. 28.

VBST efficiency in back-end mode ................. 99

Fig. 29.

VCORE schematic ........................................ 100

Fig. 30.

VCORE efficiency ..........................................103

Fig. 31.

LDOx block diagram ......................................104

Fig. 32.

VREF block diagram ..................................... 107

Fig. 33.

TRK1 and TRK2 block diagram .................... 109

Fig. 34.

Clock management block diagram ................ 111

Fig. 35.

Clock phase shifting examples ......................112

Fig. 36.

AMUX block diagram .................................... 113

Fig. 37.

WAKEx pin block diagram .............................115

Fig. 38.

GPIO1 block diagram ....................................117

Fig. 39.

GPIO2 block diagram ....................................117

Fig. 40.

GPIO low-side active high operation.

GPIOx_MODE_OTP = 0 ............................... 118

Fig. 41.

GPIO High-side Active High operation.

GPIOx_MODE_OTP = 0 ............................... 119

Fig. 42.

GPIO Push-pull Active High operation.

GPIOx_MODE_OTP = 0 ............................... 120

Fig. 43.

GPIO low-side driver Active Low operation.

GPIOx_MODE_OTP = 1 ............................... 121

Fig. 44.

VCORE PGOOD load switch ........................ 122

Fig. 45.

Long Duration Timer block diagram .............. 125

Fig. 46.

Long Duration Timer functions ...................... 128

Fig. 47.

Long duration timer state machine ................129

Fig. 48.

OTP mode time chart ....................................130

Fig. 49.

Debug mode time chart .................................131

Fig. 50.

OTP mode flowchart until safety outputs

release ...........................................................132

Fig. 51.

Debug mode flowchart until safety outputs

release ...........................................................133

Fig. 52.

Application schematic in front-end

configuration for FPRE = 450 kHz .................134

Fig. 53.

Application schematic in back-end

configuration for FPRE = 450 kHz .................135

Fig. 54.

SOT1571-6 ....................................................142

Fig. 55.

Package outline details (SOT1571-6) ............143

Fig. 56.

Package outline notes (SOT1571-6) ............. 144

Fig. 57.

PCB design guidelines - solder mask

opening pattern (SOT1571-6) ....................... 145

Fig. 58.

PCB design guidelines - I/O pads and

solderable area (SOT1571-6) ........................146

Fig. 59.

PCB design guidelines - solder paste

stencil (SOT1571-6) ...................................... 147

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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