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28HS01GTAM03 Datenblatt(PDF) 111 Page - Infineon Technologies AG

Teilenummer 28HS01GTAM03
Bauteilbeschribung  S256Mb/512Mb/1Gb SEMPER??Flash Octal interface, 1.8V/3.0V
PDF  138 Pages
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Hersteller  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

28HS01GTAM03 Datenblatt(HTML) 111 Page - Infineon Technologies AG

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002-18216 Rev. *W
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
Octal interface, 1.8V/3.0V
Timing characteristics
tSR
Internal Device Reset from Software Reset Transaction
(256T / 512T / 01GT)
90 / 83 / 83
µs
CS# Signaling Reset Timing
tCSLW
Chip Select Low
500
ns
Figure 60
tCSHG
Chip Select High
500
tRESET
Internal device reset
(HL256T / HS256T)
(HL512T / HS512T)
(HL01GT / HS01GT)
550 / 600
450 / 500
500 / 500
µs
tSUJ
Data in Setup Time (w.r.t CS#)
50
ns
tHDJ
Data in Hold Time (w.r.t CS#)
50
Embedded Algorithm (Erase, Program and Data Integrity Check) Performance[48, 49, 50, 53]
tW
nonvolatile Register Write Time
44
357.5
ms
tPP
256B Page Programming (4KB Sector / 256KB Sector)
430 / 480
2175 / 1700
µs
512B Page Programming (4KB Sector / 256KB Sector)
680 / 570
2175 / 1700
tSE
Sector Erase Time (4KB physical sectors)
42
335
ms
Sector Erase Time (256KB Infineon® Endurance Flex
architecture disabled)
773
2677
Sector Erase Time (256KB Infineon® Endurance Flex
architecture enabled)
773
5869
tBE
Chip Erase Time (256Mb)
101
348
sec
Chip Erase Time (512Mb)
201
696
Chip Erase Time (1Gb)
398
1381
tEES
Evaluate Erase Status Time for 4KB physical sectors
(HL256T / HS256T)
(HL512T / HS512T)
(HL01GT / HS01GT)
45
76 / 76
51 / 51
53 / 56
µs
Evaluate Erase Status Time for 256KB physical sectors
(HL256T / HS256T)
(HL512T / HS512T)
(HL01GT / HS01GT)
tDIC_SETUP Data Integrity Check Calculation Setup Time
(256T / 512T / 01GT)
50 / 50 /
17
µs
tDIC_RATES
Data Integrity Check Calculation Rate (Calculation rate over a
large
(>1024-byte) block of data) (256T / 512T / 01GT / 01GT)
55 / 55 / 56
65
MBps
tSEC
Sector Erase Count Time
(HL256T / HS256T)
(HL512T / HS512T)
(HL01GT / HS01GT)
55
87 / 87
63 / 63
70 / 70
µs
tBEC1
Blank Check single 256KB sector
13
17
ms
tBEC2
Blank Check single 4KB sector
12
tPASSWORD Password Comparison Time
80
100
120
µs
Program, Erase, or Data Integrity Check Suspend/Resume Timing
Table 85
Timing characteristics[45] (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Reference
figure
Notes
43. Full VCC range and CL = 15pF.
44. Output HI-Z is defined as the point where data is no longer driven.
45. Applicable across all operating temperature options.
46. If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low.
47. Sum of tRP and tRH must be equal to or greater than tRPH.
48. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V and 3.0V; checkerboard data pattern.
49. The programming time for any OTP programming transaction is the same as tPP. This includes PRSSR_4_1.
50. The programming time for the PRPPB_4_0 transaction is the same as tPP. The erase time for ERPPB_0_0 transaction is the same as tSE.
51. Values are guaranteed by characterization and not 100% tested in production.
52. Guaranteed by design.
53. The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing valid endurance
and retention tests based on a qualification specification. This methodology is intended to determine the ability of a flash device to sustain repeated
data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and retention qualifica-
tion specifications are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.



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