28HS01GTAM03 datasheet(112/138 Pages) INFINEON

112 / 138 page

Datasheet

112 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Timing characteristics

tPEDS

Program/Erase/Data Integrity Check Suspend



µs



tPEDRS

Program/Erase/Data Integrity Check Resume to next

Program/Erase/Data Integrity Check Suspend

(256T / 512T / 01GT)

250 / 

100 / 100

/ 100



Table 85

Timing characteristics[45] (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Reference

figure

Notes

43. Full VCC range and CL = 15pF.

44. Output HI-Z is defined as the point where data is no longer driven.

45. Applicable across all operating temperature options.

46. If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS# may go Low.

47. Sum of tRP and tRH must be equal to or greater than tRPH.

48. Typical program and erase times assume the following conditions: 25°C, VCC = 1.8V and 3.0V; checkerboard data pattern.

49. The programming time for any OTP programming transaction is the same as tPP. This includes PRSSR_4_1.

50. The programming time for the PRPPB_4_0 transaction is the same as tPP. The erase time for ERPPB_0_0 transaction is the same as tSE.

51. Values are guaranteed by characterization and not 100% tested in production.

52. Guaranteed by design.

53. The Joint Electron Device Engineering Council (JEDEC) standard JESD22-A117 defines the procedural requirements for performing valid endurance

and retention tests based on a qualification specification. This methodology is intended to determine the ability of a flash device to sustain repeated

data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). Endurance and retention qualifica-

tion specifications are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

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