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FS26 Datenblatt(PDF) 112 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 112 Page - NXP Semiconductors |
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112 / 156 page ![]() NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 19.1.2 Phase shifting The clocks of the switching regulators VPRE, VCORE, and VBST can be delayed to keep all the regulators from turning ON at once. This can reduce peak current and improve EMC performance. Each regulator's clock can be shifted from 1 to 3 clock cycles of the high-frequency clock (configurable by OTP). aaa-045519 55 ns 18 MHz Clock CLK1 = 2.25 MHz CLK2 = 450 kHz 55 ns 55 ns Figure 35. Clock phase shifting examples 19.1.3 Spread spectrum The internal oscillator can be modulated with a triangular carrier frequency of 23 kHz or 94 kHz, with a ±6 % deviation range around the oscillator frequency. The spread spectrum feature and the carrier frequency can be selected by SPI. The FSS_EN bit enables the spread spectrum feature and the FSS_FMOD bit selects high- or low-frequency modulation. These two bits are in the M_SYS_CFG SPI register. By default, the spread spectrum feature is disabled. The main purpose of the spread spectrum feature is to improve EMC performance by spreading out the energy of the internal oscillator and VPRE frequency. Because of this, NXP recommends enabling spread spectrum and selecting the 23 kHz carrier frequency as the default for both VPRE switching frequencies. TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages are referenced to ground. Symbol Description Min Typ Max Unit Internal oscillator High-frequency oscillator (OTP programmable) FOSC_HIGH CLK_FREQ_OTP[1:0] = 00 CLK_FREQ_OTP[1:0] = 01 CLK_FREQ_OTP[1:0] = 10 CLK_FREQ_OTP[1:0] = 11 — — — — 16 17 18 19 — — — — MHz FOSC_HIGH_ACC High-frequency oscillator accuracy -6 — 6 % FOSC_LOW Low-frequency oscillator — 98 — kHz FOSC_LOW_ACC Low-frequency oscillator accuracy -5 — 5 % Spread spectrum Spread spectrum frequency modulation for 450 kHz CLK_FREQ_OTP[1:0] = 00 (FSS_FMOD = 0, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 01 (FSS_FMOD = 0, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 10 (FSS_FMOD = 0, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 11 (FSS_FMOD = 0, FSS_EN = 1) 19.5 20.8 22.1 23.3 20.8 22.1 23.4 24.7 22.1 23.5 24.9 26.3 kHz Spread spectrum frequency modulation for 2.25 MHz FOSC_MOD CLK_FREQ_OTP[1:0] = 00 (FSS_FMOD = 1, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 01 (FSS_FMOD = 1, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 10 (FSS_FMOD = 1, FSS_EN = 1) CLK_FREQ_OTP[1:0] = 11 (FSS_FMOD = 1, FSS_EN = 1) 78.4 83.3 88.2 93.1 83.3 88.5 93.8 99 88.4 93.9 99.4 105 kHz Table 113. Clock management electrical characteristics FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 112 / 156 |
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