FS26 datasheet(116/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V, unless otherwise specified. All voltages

are referenced to ground.

Symbol

Description

Min

Typ

Max

Unit

Electrical characteristics

Low input voltage detection

VIL_WAKEx

Low voltage detection (WKxTH_OTP = 0)

High-voltage detection (WKxTH_OTP = 1)

—

0.8

0.3 * VBOS

High input voltage detection threshold

VIH_WAKEx

Low input threshold (WKxTH_OTP = 0)

High input threshold (WKxTH_OTP = 1)

0.7 * VBOS

—

VIN_HYS

Threshold hysteresis

120

500

IIN_WAKE

Input current on WAKEx pins[1]

—

µA

tWAKE

Wake-up filtering time

100

µs

Pull-down resistor on WAKE1 and WAKE2 pins

RPD_WAKE

WKxPD_SEL_OTP = 0

WKxPD_SEL_OTP = 1

100

200

320

kΩ

Table 116. Electrical characteristics

[1]

No pull-down resistor, wake-up enabled.

19.3.2 GPIO1 and GPIO2: general purpose input/output

GPIO1 pin and GPIO2 pin are general purpose input/output. They can be configured to operate as wake-up

inputs, as high-side drivers with up to 20 mA capability, or as low-side drivers with up to 2 mA capability, for use

within the ECU. GPIOx configuration can be selected with the GPIOxSTAGE_OTP[1:0] bits.

GPIO1 and GPIO2 low-side drivers can be configured to be either active high or active low with the

GPIOx_MODE_OTP bit. Active Low mode can be used to directly drive a PMOS gate without inverting the

command.

A thermal shutdown protection is implemented on GPIO1. When a thermal shutdown is triggered, GPIO1 is

automatically disabled and will remain disabled until the TSD is present (GPIO1TSD_I = 1). When the TSD is

gone (GPIO1TSD_I = 0), a SPI command is mandatory to re-enable GPIO1.

GPIOxSTAGE_OTP[1:0]

GPIOx_MODE_OTP

GPIO Configuration

Input configuration

—

Output disabled

Active High mode

Low-side driver (Active High)

Low-side driver

Active Low mode

Low-side driver (Active Low)

High-side driver

—

High-side driver (Active High)

Push-pull

—

Push-pull (Active High)

Table 117. GPIO mode configuration

An internal pull-up or pull-down can be enabled by OTP for each GPIO, depending on the

GPIOxSTAGE_OTP[1:0] configuration.. The pull-up resistor is always connected to VDDIO.

GPIO1 can be configured to keep its state in LPOFF mode or in standby mode with GPIO1LP_ON SPI bit.

GPIO2 can be configured to keep its state in standby mode with the GPIO2LP_ON bit.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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