FS26 datasheet(130/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

20 OTP and Debug mode

OTP emulation and programming performed by the customer is allowed during engineering development using

OTP mode with NXP’s latest graphical user interface and socketed evaluation board.

Customer is not allowed to perform OTP programming for production purposes. Only NXP or a recommended

third party are allowed to program the device for production purposes.

When an OTP configuration is emulated, the configuration remains available until the POR_M / POR_FS of the

digital circuitry. The fail-safe configuration is lost in low power mode (LPOFF mode and standby mode) since the

fail-safe digital is OFF in these modes.

The main digital configuration is lost when VSUP is removed, which means VBOS < VBOS_POR. When an

OTP configuration is programmed, the device will start with the programmed OTP configuration by default.

A programmed part cannot be re-programmed, but can be emulated. To enter OTP mode, the voltage at the

DEBUG pin must be set to VOTP prior to applying VSUP voltage.

During the power-up sequence, the main and the fail-safe state machines will stop prior to starting the

regulators, waiting for SPI communication to send an OTP configuration to the device. When the OTP

configuration is complete, the fail-safe state machine will start in Debug mode when the voltage at the DEBUG

pin is below VNORM_MAX (NXP recommends applying 0 V or ground).

aaa-045494

SPI OTP emulate or pgm

OFF

VDEBUG

VSUP

VWAKEx

SPI

REGx

PWR UP

PWR DWN

PWR UP

OFF

SPI OTP emulate or pgm

> VIH_WAKEx

> VSUP_UVH

VOTP

SPI

FS_LP_REQ

SPI

Figure 48. OTP mode time chart

Debug mode is intended for software debugging or first MCU programming during ECU assembly. To enter

Debug mode without first entering OTP mode, the voltage at the DEBUG pin must be set to VDBG prior to

applying the VSUP voltage. During the power-up sequence, the fail-safe state machine will start in Debug mode

and reach the initialization phase.

In Debug mode, the watchdog window is infinite opened, the RSTB 8 s counter is disabled, FS0B is maintained

low and cannot be released. The Deep Fail Safe is deactivated. The Debug mode status is reported by the

DBG_MODE bit in FS_STATES register (latched information) or by VDBG_VOLT_S in M_STATUS (real time

information). To exit Debug mode, write to the EXIT_DBG_MODE bit in the FS_STATES register.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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