FS26 datasheet(128/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

FUNCTIONS

NORMAL MODE

LOW POWER MODE (STBY/LPOFF)

Function 1

SPI: configure timer function 1

SPI: write after run register

SPI: write LDT_EN = 1

INTB when after run value reached

Timer counts

INTB

After run value reached

No entry in low power

mode controlled by LDT

Function 2

SPI: configure timer function 2

SPI: write after run register

SPI: write LDT_EN = 1

Entry in low power mode after

run value reached

Function 3

SPI: configure timer function 3

SPI: write after run register

SPI: write wake-up register

SPI: write LDT_EN = 1

Entry in low power mode after

run value reached and wake up

when wake-up value reached

Function 4

SPI: configure timer function 4

SPI: write wake-up register

SPI: write LDT_EN = 1

SPI: go to low power mode

Wake up when wake-up value

reached

Function 5

SPI: configure timer function 5

SPI: write LDT_EN = 1

SPI: go to low power mode

Wake up when other wake-up

event occurs (ex IOS)

aaa-045482

Timer counts

Wake-up

value reached

WAKE-UP

Timer counts

After run value reached

Entry in low power

mode when after run value reached

Timer counts

After run value reached

Entry in init mode

after wake up by timer

Entry in low power

mode when after run value reached

Timer counts

Wake-up

value reached

WAKE-UP

Entry in init mode

after wake up by timer

Entry in low power

mode by SPI

Timer counts

WAKE-UP (ex IOs)

Entry in init mode

after wake up by timer

Entry in low power

mode by SPI

Figure 46. Long Duration Timer functions

19.4.4 LDT operation

The timer is configured and operates with the M_LDT_CFG1, M_LDT_CFG2, M_LDT_CFG3 and

M_LDT_CTRL registers.

The 16-bit after-run value is configured and read with M_LDT_CFG1 register and the 24-bit wake-up value is

configured and read in the corresponding M_LDT_CFG2 and M_LDT_CFG3 registers.

Figure 47 describes the independent state machine for the long duration timer (LDT). After a POR_M of the

device, the LDT is in idle mode waiting for configuration. The after-run timer function starts when the LDT_EN

bit is set by SPI. The wake-up timer function starts when the device enters Low-power mode.

The LDT counter keeps the last count until the LDT is enabled again, that is, the LDT counter is reset when

LDT_EN goes from 0 to 1.

• When function 1 is selected and the counter is launched, once the after run value is reached (EOT: End of

timer) an interrupt is generated and the counter is stopped

• When function 2 is selected and the counter is launched, once the after run value is reached (EOT) the device

goes to Low-power mode and the counter is stopped.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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