FS26 datasheet(131/156 Pages) NXP

131 / 156 page

NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

aaa-045495

SPI

OFF

PWR UP

VDEBUG

VSUP

VWAKEx

SPI

REGx

PWR UP

PWR DWN OFF

> VIH_WAKEx

> VSUP_UVH

VDBG

SPI

FS_LP_REQ

Figure 49. Debug mode time chart

TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V,

unless otherwise specified. All voltages are referenced to ground.

Symbol

Description

Min

Typ

Max

Unit

Electrical characteristics

VNORM

Voltage to apply at DEBUG pin to exit OTP mode and to

start in normal mode

—

1.8

VOTP

Voltage to apply at DEBUG pin to enter OTP mode

(State machines stopped for OTP emulation/

programming)

7.4

—

8.4

VDBG

Voltage to apply at DEBUG pin to enter debug mode

(Automatic start in Debug mode with watchdog

disabled)

2.5

—

tOTP_DBG

DEBUG pin filtering time to enter OTP mode or debug

mode

µs

Table 126. Electrical characteristics

20.1 OTP mode flowchart

The diagram in Figure 50 explains the steps to enter OTP mode, emulate or program an OTP configuration,

start the fail-safe machine in Debug mode, exit Debug mode with the watchdog disabled, and release the safety

outputs.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

Document feedback

131 / 156

FS26 Datenblatt(PDF) 131 Page - NXP Semiconductors

FS26 Datenblatt(HTML) 131 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL