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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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FS26 Datenblatt(PDF) 136 Page - NXP Semiconductors |
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FS26 Datenblatt(HTML) 136 Page - NXP Semiconductors |
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136 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B 22 OTP configurations Register bitfield Register description MFS2613AMDA2AD MFS2613AMDA3AD MFS2613AMDA4AD MFS2613AMDA6AD MFS2621AMDABAD MFS2613AMDDCAD VSUP_UVTH_OTP VSUP UV threshold 4.8 V / 4.3 V 4.8 V / 4.3 V 4.8 V / 4.3 V 4.8 V / 4.3 V 4.8 V / 4.3 V 4.8 V / 4.3 V WK1DFS_DIS_OTP Exit DFS on WAKE1 event DFS exit on WAKE1 event enabled DFS exit on WAKE1 event enabled DFS exit on WAKE1 event enabled DFS exit on WAKE1 event enabled DFS exit on WAKE1 event enabled DFS exit on WAKE1 event enabled RETRY_DIS_OTP Auto-retry power-up from DFS Auto-retry enabled Auto-retry enabled Auto-retry enabled Auto-retry enabled Auto-retry enabled Auto-retry enabled RETRY_MODE_OTP Auto-retry mode Infinite retry Infinite retry Limited retry Limited retry Infinite retry Limited retry RETRY_MSK_OTP[3:0] Auto-retry timer limit 800 ms 800 ms 800 ms 800 ms 1600 ms 800 ms CLK_FREQ_OTP[1:0] Clock frequency selection 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz System configuration BOS_IN_OTP[1:0] VBOS input selection Auto Transition on VPRE_UVH Auto Transition on VPRE_UVH Auto Transition on VPRE_UVH Auto Transition on VPRE_UVH Auto Transition on VPRE_UVH Auto Transition on VPRE_UVH TSLOT_OTP[1:0] Power-up slot time 250 μs 250 μs 250 μs 250 μs 1000 μs 250 μs SLOT_BYP_OTP[2:0] Power-up slot bypass Bypass disabled Bypass disabled Bypass disabled Bypass disabled Bypass disabled Bypass disabled CORE_SLOT_OTP[2:0] VCORE power-up slot Slot 0 Slot 0 Slot 0 Slot 0 Slot 6 Slot 0 LDO1_SLOT_OTP[2:0] LDO1 power-up slot Slot 0 Slot 0 Slot 0 Slot 0 Slot 0 Slot 0 LDO2_SLOT_OTP[2:0] LDO2 power-up slot Slot 0 Slot 1 Slot 0 Slot 0 Slot 0 Slot 0 TRK1_SLOT_OTP[2:0] TRK1 power-up slot Slot 2 Slot 2 Slot 2 Slot 0 Slot 0 Slot 2 TRK2_SLOT_OTP[2:0] TRK2 power-up slot Slot 3 Slot 3 Slot 3 Slot 0 OFF Slot 3 VREF_SLOT_OTP[2:0] VREF power-up slot Slot 1 Slot 0 Slot 1 Slot 0 Slot 0 Slot 1 GPIO1_SLOT_OTP[2:0] GPIO1 power-up slot OFF Slot 4 OFF OFF Slot 1 OFF Power-up sequence GPIO2_SLOT_OTP[2:0] GPIO2 power-up slot OFF Slot 4 OFF OFF Slot 1 OFF GPIO1STAGE_OTP[1:0] GPIO configuration GPIO configured as an input Push-pull driver GPIO configured as an input GPIO configured as an input Low-side Driver GPIO configured as an input GPIO1_MODE_OTP GPIO low-side polarity GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO1PU_OTP GPIO1 pull-up Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled GPIO1PD_OTP GPIO1 pull-down Pull-down enabled Pull-down disabled Pull-down disabled Pull-down enabled Pull-down enabled Pull-down disabled GPIO1TH_OTP GPIO1 detection threshold Low-voltage threshold Low-voltage threshold Low-voltage threshold Low-voltage threshold High-voltage threshold Low-voltage threshold GPIO1TSD_PD_OTP GPIO1 TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD GPIO2STAGE_OTP[1:0] GPIO configuration Low-side driver Push-pull driver GPIO configured as an input GPIO configured as an input Low-side driver GPIO configured as an input GPIO2_MODE_OTP GPIO low-side polarity GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO LS active high GPIO2_VCORE_PGOOD_OTP GPIO2 VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO is not driven by VCORE PGOOD GPIO2PU_OTP GPIO2 pull-up Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled Pull-up disabled GPIO2PD_OTP GPIO2 pull-down Pull-down disabled Pull-down disabled Pull-down disabled Pull-down enabled Pull-down enabled Pull-down disabled GPIO2TH_OTP GPIO2 detection threshold Low-voltage threshold Low-voltage threshold Low-voltage threshold Low-voltage threshold High-voltage threshold Low-voltage threshold WK1TH_OTP WAKE1 detection threshold High-voltage threshold Low-voltage threshold High-voltage threshold Low-voltage threshold High-voltage threshold High-voltage threshold I/O configuration WK2TH_OTP WAKE2 detection threshold High-voltage threshold High-voltage threshold High-voltage threshold Low-voltage threshold High-voltage threshold High-voltage threshold Table 127. OTP configurations FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 136 / 156 |
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