 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
FS26 Datenblatt(PDF) 138 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
FS26 Datenblatt(HTML) 138 Page - NXP Semiconductors |
|
|
138 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B VCORE_OTP[7:0] VCORE voltage 1.50 V 1.50 V 1.50 V 1.50 V 1.25 V 1.50 V CORE_CTRL_OTP Control type Valley mode control Valley mode control Valley mode control Valley mode control Valley mode control Valley mode control - VCORE operating mode CCM only CCM only CCM only CCM only CCM only CCM only CORE_SS_OTP[1:0] Soft-start 5 mV/μs 10 mV/μs 10 mV/μs 5 mV/μs 5 mV/μs 20 mV/μs CORE_ILIM_OTP[1:0] VCORE current limit 2.7 A 2.7 A 1.7 A 1.7 A 2.7 A 1.7 A CORE_PH_OTP[1:0] Phase delay 2 Clock Cycles 3 Clock Cycles 2 Clock Cycles 2 Clock Cycles 2 Clock Cycles 2 Clock Cycles COREHS_SR_OTP[1:0] High-side slew rate Rise = 4.5 V/ns Fall = 1.2 V/ns Rise = 4.0 V/ns Fall = 0.6 V/ns Rise = 4.5 V/ns Fall = 1.2 V/ns Rise = 4.5 V/ns Fall = 1.2 V/ns Rise = 4.5 V/ns Fall = 1.2 V/ns Rise = 4.5 V/ns Fall = 1.2 V/ns CORE_GM_OTP[1:0] Transconductance amp 53 µS 53 µS 26 µS 26 µS 53 µS 26 µS CORE_CCOMP_OTP[1:0] Comp capacitance 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF CORE_RCOMP_OTP[1:0] Comp resistance 200 kΩ 150 kΩ 200 kΩ 200 kΩ 150 kΩ 200 kΩ CORE_LSEL_OTP[1:0] VCORE inductor 1 µH 1 µH 1 µH 1 µH 1 µH 1 µH CORETDFS_OTP TSD behavior Go to DFS Go to DFS Go to DFS Go to DFS Go to DFS Go to DFS VCORE configuration CORETSD_PD_OTP TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD VLDO1_OTP LDO1 voltage in normal mode 5.0 V 3.3 V 5.0 V 5.0 V 5.0 V 5.0 V VLDO1_LP_OTP LDO1 voltage in standby mode 5.0 V 3.3 V 5.0 V 5.0 V 5.0 V 5.0 V LDO1_LP_EN_OTP LDO1 in standby mode LDO1 enabled LDO1 disabled LDO1 enabled LDO1 enabled LDO1 enabled LDO1 enabled LDO1TDFS_OTP TSD behavior LDO1 disabled only LDO1 disabled only LDO1 disabled only LDO1 disabled only LDO1 disabled only LDO1 disabled only LDO1 configuration LDO1TSD_PD_OTP TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD VLDO2_OTP LDO2 voltage in normal mode 3.3 V 5.0 V 3.3 V 3.3 V 3.3 V 3.3 V VLDO2_LP_OTP LDO2 voltage in standby mode 3.3 V 5.0 V 3.3 V 3.3 V 3.3 V 3.3 V LDO2_LP_EN_OTP LDO2 in standby mode LDO2 enabled LDO2 enabled LDO2 enabled LDO2 enabled LDO2 enabled LDO2 enabled LDO2TDFS_OTP TSD behavior LDO2 disabled only LDO2 disabled only LDO2 disabled only LDO2 disabled only LDO2 disabled only LDO2 disabled only LDO2 configuration LDO2TSD_PD_OTP TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD TRK1_SEL_OTP[1:0] TRK1 input selection VREF LDO2 Internal LDO_REF VREF VREF Internal LDO_REF TRK1TDFS_OTP TSD behavior TRK1 disabled only TRK1 disabled only TRK1 disabled only TRK1 disabled only TRK1 disabled only TRK1 disabled only TRK1 configuration TRK1TSD_PD_OTP TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD TRK2_SEL_OTP[1:0] TRK2 input selection LDO2 LDO2 Internal LDO_REF LDO2 VREF Internal LDO_REF TRK2TDFS_OTP TSD behavior TRK2 disabled only TRK2 disabled only TRK2 disabled only TRK2 disabled only TRK2 disabled only TRK2 disabled only TRK2 configuration TRK2TSD_PD_OTP TSD pull-down Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD Pull-down enabled in TSD VREF_OTP VREF voltage 5.0 V 3.3 V 5.0 V 5.0 V 3.3 V 3.3 V VREF configuration VLDO_REF_OTP[1:0] Internal LDO reference 1.2 V 3.3 V 5.0 V 3.3 V 1.2 V 3.3 V VPRE_V_OTP[5:0] VMON_PRE monitoring voltage 6.00 V 5.40 V 6.00 V 6.00 V 6.00 V 6.00 V VMON_PRE_OVTH_OTP[3:0] VMON_PRE overvoltage threshold 110.5 % 110.5 % 110 % 110 % 110 % 110 % VMON_PRE configuration VMON_PRE_UVTH_OTP[3:0] VMON_PRE undervoltage threshold 90 % 94 % 90 % 90 % 90 % 90 % Table 127. OTP configurations...continued FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 138 / 156 |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
