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FS26 Datenblatt(PDF) 121 Page - NXP Semiconductors

Teilenummer FS26
Bauteilbeschribung  Safety system basis chip with low power for ASIL D/ASIL B
PDF  156 Pages
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FS26 Datenblatt(HTML) 121 Page - NXP Semiconductors

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NXP Semiconductors
FS26
Safety system basis chip with low power for ASIL D/ASIL B
aaa-045480
VDDIO = LDOx
VDDIO
GPIOx
out
(Slot 2)
GPIOxPU_OTP
GPIOxPD_OTP
LS OFF
STANDBY
LPOFF
OTP
loading
SLOT1
SLOT2
SLOT1
WAKE UP
EVENT
SLOT2
LP REQ
OUTPUT
Hi-Z
LDOx LP configuration
LS OFF
LS ON
Internal pullup enabled
Internal pulldown disabled
VDDIO
Figure 43. GPIO low-side driver Active Low operation. GPIOx_MODE_OTP = 1
19.3.2.4 VCORE_PGOOD: VCORE power good status
GPIO2 can be used to generate a power good signal from VMON_CORE monitoring to drive an external N-type
MOSFET to be able to start with a pre-biased voltage.
NXP recommends using an external load switch between FS26 VCORE and the MCU input supply to prevent
reverse current flow from the MCU to the VCORE regulator during low-power mode. The VCORE power good
feature can be enabled by OTP using the GPIO2_VCORE_PGOOD_OTP bit.
When GPIO2 is used as VCORE_PGOOD, the HS switch (connected internally to VPRE) is used to close
the external N-type MOSFET. The power good signal is released as soon as VMON_CORE crosses its
undervoltage threshold. VCORE_PGOOD is asserted low when VCORE is disabled, or when an error is
reported from VMON_CORE voltage monitoring (undervoltage or overvoltage). Therefore, VCORE_PGOOD
will be asserted low when entering Low power mode, setting the CORE_UV flag as soon as the Fail-safe state
machine disables VMON_CORE voltage monitoring block, despite VCORE being still up and running.
An external pulldown is mandatory to assert the pin low when the high-side switch is turned off.
FS26_SDS
All information provided in this document is subject to legal disclaimers.
© 2025 NXP B.V. All rights reserved.
Product short data sheet
Rev. 6.0 — 12 December 2025
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