FS26 datasheet(125/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

TA = –40 °C to 125 °C, unless otherwise specified. VSUP_UVH < VSUP < 36 V, VPRE_PWM + VPRE_HDR < VSUP_PWR < 36 V,

unless otherwise specified. All voltages are referenced to ground.

Symbol

Description

Min

Typ

Max

Unit

Electrical characteristics

RINTB_PU

Internal pull-up resistor to VDDIO

kΩ

VINTB_VOL

Low output level threshold

IINTB = 2.0 mA

—

0.4

INTB_LEAK

Input leakage current

VDDIO = 5.5 V

—

1.0

µA

IINTB_ILIM

INTB current limitation

—

Interrupt pulse duration

tINTB_PULSE

Short pulse (INT_PWIDTH = 0)

Long pulse (INT_PWIDTH = 1)

17.5

100

32.5

130

µs

Table 123. INTB Electrical characteristics

19.4 LDT: long duration timer

The FS26 features a long duration timer (LDT) with an integrated oscillator. The timer is configurable by the

SPI and can operate in normal mode and in Low-power modes. It provides several functions and offers a wide

range of configurable counting periods, as well as a calibration mechanism for internal oscillator compensation

(function1).

The timer is not part of the safety circuitry and is not covered by LBIST (logic built-in self-test). It can be

activated in normal mode, though, and all prescaler options can be selected to allow timer circuitry verification.

The timer is based on a 24 bit counter, with a 32768 Hz oscillator, allowing a 1.0 second time base.

aaa-045520

32 kHz

OSC

PRESCALER 1

(/16)

24-bit COUNTER

CONTROL REGISTER

READ

to internal:

mode change

(LPOFF, WU)

COMP.

MISO

MOSI

SCLK

CSB

INT

24 bits: WAKE UP

16 bits: AFTER RUN

PRESCALER 2

(/2048)

EXTERNAL

(calibration)

30 µs

488 µs

1.0 s (cal: 488 µs)

Figure 45. Long Duration Timer block diagram

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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