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28HS01GTAM03 Datenblatt(PDF) 122 Page - Infineon Technologies AG |
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28HS01GTAM03 Datenblatt(HTML) 122 Page - Infineon Technologies AG |
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122 / 138 page ![]() Datasheet 122 of 138 002-18216 Rev. *W 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash Octal interface, 1.8V/3.0V Device identification 160h JEDEC xSPI Profile 1.0 DWORD-3 00h Bits 7:0 = Reserved = 00h 161h B0h Bit 31 = Read SFDP 8D-8D-8D command supported = 1b Bit 30 = Read Fast Wrapped command not supported = 0b Bit 29 = Setup Read Wrap command not supported = 0b Bit 28 = Erase 4KB command supported = 1b Bit 27 = Erase 32KB command not supported = 0b Bit 26 = Erase Chip command supported = 1b Bit 25 = Read Configuration Register command supported = 1b Bit 24 = Read Flag Status Register command not supported = 0b Bit 23 = Read Register command supported = 1b Bit 22 = Read Volatile Register command supported = 1b Bit 21 = Read NV Register command supported = 1b Bit 20 = Write Status-Configuration Register command supported = 1b Bit 19 = Clear Flag Status Reg command supported = 1b Bit 18 = Write Register command supported = 1b Bit 17 = Write volatile register command supported = 1b Bit 16 = Write NV register command supported = 1b Bit 15 = Enter Deep Power Down command not supported = 1b Bit 14 = Exit Deep Power Down command not supported = 0b Bit 13 = Soft Reset command supported = 1b Bit 12 = Reset Enable command supported = 1b Bit 11 = Soft Reset and Enter default protocol mode command supported = 0b Bit 10 = Enter default protocol mode command not supported = 0b Bits 9:8 = Reserved = 00b 162h FFh 163h 96h 164h JEDEC xSPI Profile 1.0 DWORD-4 A8h Bits 31:12 = 00000h Bits 11:7 = 200MHz operation: number of dummy cycles required = 23 = 10111b Bit 6:2 = 200MHz operation: configuration bit pattern to set this number of dummy cycles = 01010b Bits 1:0 = Reserved = 00b 165h 0Bh 166h 00h 167h 00h 168h JEDEC xSPI Profile 1.0 DWORD-5 0Ch Bits 31:27 = 166MHz operation: number of dummy cycles required = 20 = 10100b Bit 26:22 = 166MHz operation: configuration bit pattern to set this number of dummy cycles = 01000b Bits 21:17 = 133MHz operation: number of dummy cycles required = 14 = 01110b Bit 16:12 = 133MHz operation: configuration bit pattern to set this number of dummy cycles = 00101b Bits 11:7 = 100MHz operation: number of dummy cycles required = 10 = 01010b Bit 6:2 = 100MHz operation: configuration bit pattern to set this number of dummy cycles = 00011b Bits 1:0 = Reserved = 00b 169h 55h 16Ah 1Ch 16Bh A2h 16Ch Status, Control and Configuration Register Map DWORD-1 00h Bits 31:0 = Address offset for volatile registers = 00800000h 16Dh 00h 16Eh 80h 16Fh 00h 170h Status, Control and Configuration Register Map DWORD-2 00h Bits 31:0 = Address offset for nonvolatile registers = 00000000h 171h 00h 172h 00h 173h 00h 174h Status, Control and Configuration Register Map DWORD-3 C0h Bit 31 = Generic Addressable Read Status/Control register command for volatile registers supported for some (or all) registers = 1b Bit 30 = Generic Addressable Write Status/Control register command for volatile registers supported for some (or all) registers = 1b Bits 29:28 = Number of address bytes used for Generic Addressable Read/Write Status/Control register commands for volatile registers = 3 byte (default) = 10b Bit 27:26 = Number of dummy bytes used for Generic Addressable Read Status/Control register command for volatile registers in (1S-1S-1S) mode = 10b Bit 25:14 = Not supported = FFFh Bit 13:10 = Number of dummy cycles used for Generic Addressable Read Status/Control register command for volatile registers in (8S-8S-8S) mode = 3 = 0011b Bit 9:6 = Number of dummy cycles used for Generic Addressable Read Status/Control register command for volatile registers in (8D-8D-8D) mode = 3 = 0011b Bit 5:4 = Reserved = 00b Bit 3:0 = Number of dummy cycles used for Generic Addressable Read Status/Control register command for volatile registers in (1S-1S-1S) mode = 0000b 175h CCh 176h FFh 177h EBh Table 87 JEDEC SFDP Rev D parameter table (Continued) SFDP byte address SFDP DWORD name Data Description |
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