28HS01GTAM03 datasheet(124/138 Pages) INFINEON

124 / 138 page

Datasheet

124 of 138

002-18216 Rev. *W

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

Octal interface, 1.8V/3.0V

Device identification

190h

Status, Control and

Configuration Register

Map DWORD-10

71h

Bits 7:0 = Command used for write access = 71h

191h

65h

Bits 15:8 = Command used for read access = 65h

192h

03h

Address of register where wait states bits are located = 03h (Configuration Reg - 2

nonvolatile)

193h

D0h

Bit 31 = Variable number of dummy cycles supported = 1b

Bits 30:29 = Number of physical bits used to set wait states - 4 bit = 10b

Bits 28 = Bit is set/cleared by commands using address = 1b

Bit 27 = Not Supported = 0b

Bits 26:24 = Bit location of LSB of physical bits in register = bit [0] = 000b

194h

Status, Control and

Configuration Register

Map DWORD-11

A4h

Bit 31 = 30 dummy cycles supported = 0b

Bit 30:26 = Bit pattern used to set 30 dummy cycles = 00000b

Bit 25 = 28 dummy cycles supported = 1b

Bit 24:20 = Bit pattern used to set 28 dummy cycles = 01111b

Bit 19 = 26 dummy cycles supported = 1b

Bit 18:14 = Bit pattern used to set 26 dummy cycles = 01101b

Bit 13 = 24 dummy cycles supported = 1b

Bit 12:8 = Bit pattern used to set 24 dummy cycles = 01011b

Bit 7 = 22 dummy cycles supported = 1b

Bit 6:2 = Bit pattern used to set 22 dummy cycles = 01001b

Bits 1:0 = Reserved = 00b

195h

6Bh

196h

FBh

197h

02h

198h

Status, Control and

Configuration Register

Map DWORD-12

90h

Bit 31 = 20 dummy cycles supported = 1b

Bit 30:26 = Bit pattern used to set 20 dummy cycles = 01000b

Bit 25 = 18 dummy cycles supported = 1b

Bit 24:20 = Bit pattern used to set 18 dummy cycles = 00111b

Bit 19 = 16 dummy cycles supported = 1b

Bit 18:14 = Bit pattern used to set 16 dummy cycles = 00110b

Bit 13 = 14 dummy cycles supported = 1b

Bit 12:8 = Bit pattern used to set 14 dummy cycles = 00101b

Bit 7 = 12 dummy cycles supported = 1b

Bit 6:2 = Bit pattern used to set 12 dummy cycles = 00100b

Bits 1:0 = Reserved = 00b

199h

A5h

19Ah

79h

19Bh

A2h

19Ch

Status, Control and

Configuration Register

Map DWORD-13

00h

Bit 31 = 10 dummy cycles supported = 1b

Bit 30:26 = Bit pattern used to set 10 dummy cycles = 00011b

Bit 25 = 8 dummy cycles supported = 1b

Bit 24:20 = Bit pattern used to set 8 dummy cycles = 00010b

Bit 19 = 6 dummy cycles supported = 1b

Bit 18:14 = Bit pattern used to set 6 dummy cycles = 00001b

Bit 13 = 4 dummy cycles supported = 0b

Bit 12:8 = Bit pattern used to set 4 dummy cycles = 00000b

Bit 7 = 2 dummy cycles supported = 0b

Bit 6:2 = Bit pattern used to set 2 dummy cycles = 00000b

Bits 1:0 = Reserved = 00b

19Dh

40h

19Eh

28h

19Fh

8Eh

1A0h

Status, Control and

Configuration Register

Map DWORD-14

00h

Not Supported

1A1h

00h

1A2h

FFh

1A3h

00h

1A4h

Status, Control and

Configuration Register

Map DWORD-15

00h

Not Supported

1A5h

00h

1A6h

FFh

1A7h

00h

1A8h

Status, Control and

Configuration Register

Map DWORD-16

71h

Bits 7:0 = Command used for write access = 71h

1A9h

65h

Bits 15:8 = Command used for read access = 65h

1AAh

06h

Bits 23:16 = Address of register where Octal Mode Enable volatile bit is located =

800006h

(Configuration Reg - 5 volatile)

1ABh

90h

Bit 31 = Octal Mode Enable volatile bit supported = 1b

Bits 30 = Octal Mode Enable volatile bit polarity: Positive (Octal Mode Enable bit = 1

indicates Octal mode is enabled) = 0b

Bits 29 = Reserved = 0b

Bits 28 = Bit is set/cleared by commands using address = 1b

Bit 27 = Not supported = 0b

Bits 26:24 = Bit location of Octal Mode enable bit in register = bit [0] = 000b

Table 87

JEDEC SFDP Rev D parameter table (Continued)

SFDP byte address

SFDP DWORD name

Data

Description

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